Patent search cpc:"H01L2924/10346" Page 2

11.

发明授权
III-nitride device and FET in a package 有权
Title translation: III族氮化物器件和封装中的FET

公开(公告)号：US09312245B2

公开(公告)日：2016-04-12

申请号：US14496140

申请日：2014-09-25

Applicant: International Rectifier Corporation

Inventor： Heny Lin , Jason Zhang , Alberto Guerra

IPC: H01L25/07 , H01L27/20 , H01L23/495 , H01L29/20 , H01L29/16 , H01L29/772 , H01L23/00 , H01L29/778

CPC classification number: H01L25/074 , H01L23/49562 , H01L23/49575 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/69 , H01L24/72 , H01L24/73 , H01L29/16 , H01L29/2003 , H01L29/772 , H01L29/778 , H01L2224/0603 , H01L2224/2919 , H01L2224/32145 , H01L2224/32245 , H01L2224/45014 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48145 , H01L2224/48247 , H01L2224/49111 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06568 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/10253 , H01L2924/10323 , H01L2924/1033 , H01L2924/10334 , H01L2924/10344 , H01L2924/10346 , H01L2924/1306 , H01L2924/15787 , H01L2924/30107 , H01L2924/00 , H01L2924/00012 , H01L2224/85399 , H01L2224/05599

Abstract: One exemplary disclosed embodiment comprises a three-terminal stacked-die package including a field effect transistor (PET), such as a silicon PET, stacked atop a III-nitride transistor, such that a drain of the PET resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a gate of the FET, a second terminal of the package is coupled to a drain of the III-nitride transistor. A third terminal of the package is coupled to a source of the FET. In this manner, devices such as cascoded switches may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages.

Abstract translation: 一个示例性的公开的实施例包括三端子堆叠管芯封装，其包括层叠在III族氮化物晶体管的顶部的诸如硅PET的场效应晶体管（PET），使得PET的漏极位于电耦合到 III族氮化物晶体管的源极。封装的第一端子耦合到FET的栅极，封装的第二端子耦合到III族氮化物晶体管的漏极。封装的第三端子耦合到FET的源极。以这种方式，诸如级联开关的器件可以以堆叠的管芯形式被封装，从而与常规封装相比，减小了寄生电感和电阻，改善的散热，更小的外形尺寸和更低的制造成本。

12.

发明申请
Method for Fabricating a Semiconductor Package with Conductive Carrier Integrated Heat Spreader 有权
Title translation: 用导电载体集成散热器制造半导体封装的方法

公开(公告)号：US20150348887A1

公开(公告)日：2015-12-03

申请号：US14825382

申请日：2015-08-13

Applicant: International Rectifier Corporation

Inventor： Eung San Cho , Andrew N. Sawle , Mark Pavier , Daniel Cutler

IPC: H01L23/495 , H01L25/07 , H01L23/00 , H01L25/00

CPC classification number: H01L21/84 , H01L21/4825 , H01L21/4871 , H01L21/561 , H01L23/3121 , H01L23/49562 , H01L23/49568 , H01L23/49575 , H01L24/16 , H01L24/24 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/82 , H01L24/83 , H01L24/92 , H01L25/072 , H01L25/117 , H01L25/16 , H01L25/18 , H01L25/50 , H01L2224/16245 , H01L2224/24137 , H01L2224/24245 , H01L2224/29101 , H01L2224/2929 , H01L2224/32245 , H01L2224/73259 , H01L2224/73267 , H01L2224/8382 , H01L2224/8384 , H01L2224/92224 , H01L2224/92244 , H01L2924/10253 , H01L2924/10323 , H01L2924/10325 , H01L2924/1033 , H01L2924/10334 , H01L2924/10341 , H01L2924/10344 , H01L2924/10346 , H01L2924/10355 , H01L2924/10356 , H01L2924/10357 , H01L2924/10358 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/1426 , H01L2924/1815 , H01L2924/00 , H01L2924/0665 , H01L2924/00014 , H01L2924/014

Abstract: In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage having a control drain attached to the die side of the control conductive carrier. The control conductive carrier is configured to sink heat produced by the control FET into the mounting surface. The semiconductor package includes a sync conductive carrier having another die side and another opposite I/O side connecting the semiconductor package to the mounting surface, and a sync FET of the power converter switching stage having a sync source attached to the die side of the sync conductive carrier.

Abstract translation: 在一个实施方案中，半导体封装包括具有裸片侧的控制导电载体和将半导体封装连接到安装表面的相反的输入/输出（I / O）侧。半导体封装还包括功率转换器开关级的控制FET，其具有附着到控制导电载体的管芯侧的控制漏极。控制导电载体被配置为将由控制FET产生的热量吸收到安装表面中。半导体封装包括具有另一管芯侧的同步导电载体和将半导体封装连接到安装表面的另一相对I / O侧，以及功率转换器开关级的同步FET，其具有连接到同步的管芯侧的同步源导电载体。

13.

发明申请
Semiconductor Device with a Passivation Layer and Method for Producing Thereof 审中-公开
Title translation: 具有钝化层的半导体器件及其制造方法

公开(公告)号：US20150255362A1

公开(公告)日：2015-09-10

申请号：US14200732

申请日：2014-03-07

Applicant: Infineon Technologies AG

Inventor： Jens Peter Konrath , Christian Hecht , Roland Rupp , Andre Kabakow

IPC: H01L23/31 , H01L29/872 , H01L29/808 , H01L29/78 , H01L21/56 , H01L21/308 , H01L29/66 , H01L27/06 , H01L23/29 , H01L29/47 , H01L21/283 , H01L21/02 , H01L21/28 , H01L29/70

CPC classification number: H01L23/3171 , H01L21/02126 , H01L21/02129 , H01L21/02164 , H01L21/0217 , H01L21/28247 , H01L21/283 , H01L21/3081 , H01L21/56 , H01L23/29 , H01L23/3192 , H01L27/0629 , H01L29/0615 , H01L29/0619 , H01L29/0638 , H01L29/0661 , H01L29/1066 , H01L29/4236 , H01L29/47 , H01L29/66674 , H01L29/66901 , H01L29/70 , H01L29/7397 , H01L29/7801 , H01L29/7811 , H01L29/7813 , H01L29/808 , H01L29/8083 , H01L29/8611 , H01L29/872 , H01L2224/05567 , H01L2224/05624 , H01L2224/05647 , H01L2224/05666 , H01L2924/10272 , H01L2924/10329 , H01L2924/1033 , H01L2924/10331 , H01L2924/10335 , H01L2924/10346 , H01L2924/10373 , H01L2924/13055 , H01L2924/13062 , H01L2924/13091 , H01L2924/00

Abstract: A semiconductor device includes a semiconductor body having a first surface, a contact electrode on the first surface, and a passivation layer on the first surface adjacent the contact electrode and partially overlapping the contact electrode. The passivation layer comprises a layer stack with a first layer comprising an oxide on the first surface, and a second layer comprising a nitride on the first layer.

Abstract translation: 半导体器件包括具有第一表面的半导体本体，第一表面上的接触电极和与接触电极相邻的第一表面上的钝化层，并且部分地与接触电极重叠。钝化层包括具有在第一表面上包含氧化物的第一层的层叠层，以及在第一层上包含氮化物的第二层。

14.

发明授权
High power semiconductor package with conductive clip 有权
Title translation: 大功率半导体封装，带导电夹

公开(公告)号：US08896107B2

公开(公告)日：2014-11-25

申请号：US13095146

申请日：2011-04-27

Applicant: Eung San Cho , Chuan Cheah

Inventor： Eung San Cho , Chuan Cheah

IPC: H01L23/495 , H01L23/34 , H01L23/00

CPC classification number: H01L23/49517 , H01L23/49524 , H01L23/49562 , H01L23/49575 , H01L24/37 , H01L24/40 , H01L24/48 , H01L24/49 , H01L25/165 , H01L2224/0603 , H01L2224/371 , H01L2224/37147 , H01L2224/40095 , H01L2224/40245 , H01L2224/48091 , H01L2224/48106 , H01L2224/48137 , H01L2224/48247 , H01L2224/49111 , H01L2224/84801 , H01L2224/8485 , H01L2924/00014 , H01L2924/01029 , H01L2924/10323 , H01L2924/1033 , H01L2924/10334 , H01L2924/10344 , H01L2924/10346 , H01L2924/13091 , H01L2924/14 , H01L2924/1426 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2924/00012 , H01L2224/45099

Abstract: One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor, a sync transistor, a driver integrated circuit (IC) for driving the control and sync transistors, and a conductive clip electrically coupling a sync drain of the sync transistor to a first leadframe pad of the package, wherein the first leadframe pad of the package is electrically coupled to a control source of the control transistor using a wirebond. The conductive clip provides an efficient connection between the control source and the sync drain by direct mechanical connection and large surface area conduction. A sync source is electrically and mechanically coupled to a second leadframe pad providing a high current carrying capability, and high reliability. The resulting package has significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections.

Abstract translation: 一个示例性的公开的实施例包括被配置为具有控制晶体管，同步晶体管，用于驱动控制和同步晶体管的驱动器集成电路（IC））的降压转换器的高功率半导体封装，以及电连接同步晶体管耦合到封装的第一引线框焊盘，其中封装的第一引线框焊盘使用引线键电耦合到控制晶体管的控制源。导电夹子通过直接机械连接和大的表面积传导提供控制源和同步排放之间的有效连接。同步源电和机械地耦合到提供高电流承载能力的第二引线框架，并且具有高可靠性。与使用用于晶体管互连的引线的常规封装方法相比，所得封装具有显着降低的电阻，外形尺寸，复杂性和成本。

15.

发明授权
III-nitride transistor stacked with FET in a package 有权
Title translation: 在封装中堆叠有FET的III族氮化物晶体管

公开(公告)号：US08847408B2

公开(公告)日：2014-09-30

申请号：US13053556

申请日：2011-03-22

Applicant: Heny Lin , Jason Zhang , Alberto Guerra

Inventor： Heny Lin , Jason Zhang , Alberto Guerra

IPC: H01L25/18 , H01L23/495 , H01L23/00 , H01L29/20 , H01L29/778

CPC classification number: H01L25/074 , H01L23/49562 , H01L23/49575 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/69 , H01L24/72 , H01L24/73 , H01L29/16 , H01L29/2003 , H01L29/772 , H01L29/778 , H01L2224/0603 , H01L2224/2919 , H01L2224/32145 , H01L2224/32245 , H01L2224/45014 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48145 , H01L2224/48247 , H01L2224/49111 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06568 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/10253 , H01L2924/10323 , H01L2924/1033 , H01L2924/10334 , H01L2924/10344 , H01L2924/10346 , H01L2924/1306 , H01L2924/15787 , H01L2924/30107 , H01L2924/00 , H01L2924/00012 , H01L2224/85399 , H01L2224/05599

Abstract: One exemplary disclosed embodiment comprises a three-terminal stacked-die package including a field effect transistor (FET), such as a silicon FET, stacked atop a III-nitride transistor, such that a drain of the FET resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a gate of the FET, a second terminal of the package is coupled to a drain of the III-nitride transistor. A third terminal of the package is coupled to a source of the FET. In this manner, devices such as cascoded switches may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages.

Abstract translation: 一个示例性的公开的实施例包括三端堆叠管芯封装，其包括堆叠在III族氮化物晶体管顶部的场效应晶体管（FET），例如硅FET，使得FET的漏极驻留在电耦合到 III族氮化物晶体管的源极。封装的第一端子耦合到FET的栅极，封装的第二端子耦合到III族氮化物晶体管的漏极。封装的第三端子耦合到FET的源极。以这种方式，诸如级联开关的器件可以以堆叠的管芯形式被封装，从而与常规封装相比，减小了寄生电感和电阻，改善的散热，更小的外形尺寸和更低的制造成本。

16.

发明授权
High power semiconductor package with conductive clip and flip chip driver IC with integrated control transistor 有权
Title translation: 大功率半导体封装，带导电夹和倒装芯片驱动IC，集成控制晶体管

公开(公告)号：US08749034B2

公开(公告)日：2014-06-10

申请号：US13095725

申请日：2011-04-27

Applicant: Eung San Cho , Chuan Cheah

Inventor： Eung San Cho , Chuan Cheah

IPC: H01L23/495 , H01L23/52 , H01L23/34 , H01L23/48 , H01L29/40

CPC classification number: H01L23/49517 , H01L23/49524 , H01L23/49562 , H01L23/49575 , H01L24/37 , H01L24/40 , H01L24/48 , H01L24/49 , H01L25/165 , H01L2224/0603 , H01L2224/371 , H01L2224/37147 , H01L2224/40095 , H01L2224/40245 , H01L2224/48091 , H01L2224/48106 , H01L2224/48137 , H01L2224/48247 , H01L2224/49111 , H01L2224/84801 , H01L2224/8485 , H01L2924/00014 , H01L2924/01029 , H01L2924/10323 , H01L2924/1033 , H01L2924/10334 , H01L2924/10344 , H01L2924/10346 , H01L2924/13091 , H01L2924/14 , H01L2924/1426 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2924/00012 , H01L2224/45099

Abstract: One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a sync transistor with a top surface having a drain, a flip chip driver integrated circuit (IC) having an integrated control transistor, the flip chip driver IC driving the sync and control transistors, and a conductive clip electrically coupling the drain of the sync transistor to a common portion of the leadframe shared with a control source of the control transistor. In this manner, the leadframe and the conductive clip provide efficient current conduction by direct mechanical connection and large surface area conduction, significantly reducing package electrical resistance, form factor, complexity, and cost compared to conventional packages. Moreover, by integrating only the control transistor rather than both the control and sync transistor within the flip chip driver IC, the sync transistor may remain separate, simplifying manufacture and providing greater total surface area for thermal dissipation.

Abstract translation: 一个示例性的公开实施例包括被配置为降压转换器的大功率半导体封装，具有具有漏极的顶表面的同步晶体管，具有集成控制晶体管的倒装芯片驱动器集成电路（IC），所述倒装芯片驱动器IC驱动同步和控制晶体管，以及将同步晶体管的漏极电耦合到与控制晶体管的控制源共享的引线框架的公共部分的导电夹。以这种方式，与常规封装相比，引线框架和导电夹具通过直接机械连接和大的表面积传导提供有效的电流传导，显着降低封装电阻，外形尺寸，复杂性和成本。而且，通过在倒装芯片驱动器IC内只集成控制晶体管而不是控制和同步晶体管两者，同步晶体管可以保持分离，简化制造并提供更大的总体表面积用于散热。

17.

发明授权
High power semiconductor package with conductive clips and flip chip driver IC 有权
Title translation: 大功率半导体封装，带导电夹和倒装芯片驱动IC

公开(公告)号：US08497574B2

公开(公告)日：2013-07-30

申请号：US13095650

申请日：2011-04-27

Applicant: Eung San Cho , Chuan Cheah

Inventor： Eung San Cho , Chuan Cheah

IPC: H01L23/495

CPC classification number: H01L23/49517 , H01L23/49524 , H01L23/49562 , H01L23/49575 , H01L24/37 , H01L24/40 , H01L24/48 , H01L24/49 , H01L25/165 , H01L2224/0603 , H01L2224/371 , H01L2224/37147 , H01L2224/40095 , H01L2224/40245 , H01L2224/48091 , H01L2224/48106 , H01L2224/48137 , H01L2224/48247 , H01L2224/49111 , H01L2224/84801 , H01L2224/8485 , H01L2924/00014 , H01L2924/01029 , H01L2924/10323 , H01L2924/1033 , H01L2924/10334 , H01L2924/10344 , H01L2924/10346 , H01L2924/13091 , H01L2924/14 , H01L2924/1426 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2924/00012 , H01L2224/45099

Abstract: In one implementation, a high power semiconductor package is configured as a buck converter including a control transistor and a sync transistor disposed on a leadframe, a flip chip driver integrated circuit (IC) for driving the control and sync transistors, and conductive clips electrically coupling the top surfaces of the transistors to substrate pads such as leadframe pads. The source of the control transistor is electrically coupled to the drain of the sync transistor using the leadframe and one of the transistor conductive clips. In this manner, the leadframe and the conductive clips provide efficient current conduction by direct mechanical connection and large surface area conduction, thereby enabling a package with significantly reduced electrical resistance, form factor, complexity, and cost.

Abstract translation: 在一个实现中，大功率半导体封装被配置为降压转换器，其包括设置在引线框上的控制晶体管和同步晶体管，用于驱动控制和同步晶体管的倒装芯片驱动器集成电路（IC）以及电耦合的导电夹晶体管的顶表面到衬底焊盘，例如引线框焊盘。使用引线框和晶体管导电夹中的一个，控制晶体管的源极电耦合到同步晶体管的漏极。以这种方式，引线框架和导电夹子通过直接机械连接和大的表面积传导提供有效的电流传导，从而使得具有显着降低的电阻，形状因子，复杂性和成本的封装。

18.

发明授权
Packaging for RF transistor amplifiers 有权

公开(公告)号：US11837457B2

公开(公告)日：2023-12-05

申请号：US17018721

申请日：2020-09-11

Applicant: Cree, Inc.

Inventor： Basim Noori , Marvin Marbell , Scott Sheppard , Kwangmo Chris Lim , Alexander Komposch , Qianli Mu

IPC: H01L23/538 , H01L23/498 , H01L23/66 , H01L23/00 , H01L25/16 , H01L25/00 , H01L29/417 , H01L29/423

CPC classification number: H01L23/5389 , H01L23/49811 , H01L23/5386 , H01L23/66 , H01L24/16 , H01L24/32 , H01L25/16 , H01L25/50 , H01L29/41741 , H01L29/4238 , H01L2223/6644 , H01L2223/6655 , H01L2224/16227 , H01L2224/32245 , H01L2924/1033 , H01L2924/10253 , H01L2924/10272 , H01L2924/10344 , H01L2924/10346 , H01L2924/13064 , H01L2924/19105

Abstract: RF transistor amplifiers an RF transistor amplifier die having a semiconductor layer structure, an interconnect structure having first and second opposing sides, wherein the first side of the interconnect structure is adjacent a surface of the RF transistor amplifier die such that the interconnect structure and the RF transistor amplifier die are in a stacked arrangement, and one or more circuit elements on the first and/or second side of the interconnect structure.

19.

发明授权
Wafer structure and method for wafer dicing 有权

公开(公告)号：US09748187B2

公开(公告)日：2017-08-29

申请号：US14577141

申请日：2014-12-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yueh-Chuan Lee , Chia-Chan Chen

IPC: H01L23/02 , H01L23/00 , H01L23/58 , H01L21/78 , H01L21/306

CPC classification number: H01L24/06 , H01L21/30604 , H01L21/78 , H01L23/585 , H01L24/03 , H01L24/94 , H01L33/0095 , H01L2224/05016 , H01L2224/06179 , H01L2924/10252 , H01L2924/10253 , H01L2924/10271 , H01L2924/10329 , H01L2924/1033 , H01L2924/10331 , H01L2924/10335 , H01L2924/10336 , H01L2924/10338 , H01L2924/10342 , H01L2924/10346 , H01L2924/2064

Abstract: The semiconductor die includes a base body, protruding portions and bonding pads. The base body has sidewalls. The protruding portions are laterally protruding from the sidewalls respectively. The bonding pads are disposed on the protruding portions respectively. The wafer dicing method includes following operations. Chips are formed on a semiconductor wafer. Bonding pads are formed on a border line between every two of the adjacent chips. A scribe line is formed and disposed along the bonding pads. A photolithographic pattern is formed on a top surface of the semiconductor wafer to expose the scribe line. The scribe line is etched to a depth in the semiconductor wafer substantially below the top surface layer to form an etched pattern. A back surface of the semiconductor wafer is thinned until the etched pattern in the wafer substrate is exposed.