公开(公告)号：US12057362B2

公开(公告)日：2024-08-06

申请号：US17349211

申请日：2021-06-16

申请人： ROHM CO., LTD.

发明人： Osamu Miyata ,  Masaki Kasai ,  Shingo Higuchi

IPC分类号： H01L23/48 ,  H01L21/78 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/528 ,  H01L23/544

CPC分类号： H01L23/3178 ,  H01L21/78 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3142 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/528 ,  H01L23/544 ,  H01L23/562 ,  H01L24/02 ,  H01L24/10 ,  H01L24/13 ,  H01L24/94 ,  H01L24/96 ,  H01L24/05 ,  H01L2223/5446 ,  H01L2224/02255 ,  H01L2224/0226 ,  H01L2224/02377 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/10161 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/182 ,  H01L2924/186 ,  H01L2924/3025 ,  H01L24/13 ,  H01L2924/00 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2224/13 ,  H01L2924/00 ,  H01L2224/0239 ,  H01L2924/01029 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2224/05571 ,  H01L2924/00012 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05124 ,  H01L2924/00014

摘要： A semiconductor device includes a semiconductor chip having a passivation film, a stress relieving layer provided on the passivation film, and a groove formed in a periphery of a surface of the semiconductor chip, the groove being provided inside of an edge of the semiconductor chip, wherein the stress relieving layer is partly disposed in the groove.

公开(公告)号：US12057324B2

公开(公告)日：2024-08-06

申请号：US18090918

申请日：2022-12-29

申请人： Shanghai Tianma Micro-Electronics Co., Ltd. ,  Shanghai AVIC OPTO Electronics Co., Ltd.

发明人： Xuhui Peng ,  Kerui Xi ,  Tingting Cui ,  Feng Qin ,  Jie Zhang

IPC分类号： H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498

CPC分类号： H01L21/4853 ,  H01L21/486 ,  H01L21/4896 ,  H01L21/561 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L2924/37001

摘要： A semiconductor package includes a semiconductor element, a wiring structure, an encapsulation structure, and a solder ball. The semiconductor element includes a plurality of pins. A side of the wiring structure is electrically connected to the plurality of pins of the semiconductor element. The wiring structure includes at least two first wiring layers. A first insulating layer is disposed between adjacent two first wiring layers of the at least two first wiring layers. The first insulating layer includes a plurality of first through-holes. The adjacent two first wiring layers are electrically connected to each other through the plurality of first through-holes. The encapsulation structure at least partially surrounds the semiconductor element. The solder ball is located on a side of the wiring structure away from the semiconductor element. The solder ball is electrically connected to the at least two first wiring layers.

公开(公告)号：US12046548B2

公开(公告)日：2024-07-23

申请号：US18307091

申请日：2023-04-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shin-Puu Jeng ,  Po-Hao Tsai ,  Po-Yao Chuang ,  Feng-Cheng Hsu ,  Shuo-Mao Chen ,  Techi Wong

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L21/52 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/053 ,  H01L25/00 ,  H01L25/10 ,  H01L23/31

CPC分类号： H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/52 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/053 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/96 ,  H01L25/105 ,  H01L25/50 ,  H01L21/561 ,  H01L23/3128 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2224/0401 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/26175 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/83191 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/15311 ,  H01L2224/97 ,  H01L2224/81 ,  H01L2224/97 ,  H01L2224/83

摘要： A chip package is provided. The chip package includes a substrate structure. The substrate structure includes a redistribution structure having a conductive pad. The substrate structure includes a first insulating layer under the redistribution structure. The substrate structure includes a conductive via structure passing through the first insulating layer. The conductive via structure is under and electrically connected with the conductive pad. The substrate structure includes a second insulating layer disposed between the redistribution structure and the first insulating layer. The chip package includes a first chip over the redistribution structure and electrically connected to the conductive via structure through the redistribution structure. The chip package includes a second chip under the substrate structure.

公开(公告)号：US20240234335A1

公开(公告)日：2024-07-11

申请号：US18310629

申请日：2023-05-02

申请人： SILICONWARE PRECISION INDUSTRIES CO., LTD.

发明人： Yen-Yu CHU ,  Tsung-Yu HUANG ,  Kuo-Hua TSENG ,  Tsung-Xin CHIEN ,  Chang-Ku-Yuan SIE

IPC分类号： H01L23/552 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/367 ,  H01L25/065 ,  H01L25/16

CPC分类号： H01L23/552 ,  H01L21/4882 ,  H01L21/561 ,  H01L23/3675 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/165 ,  H01L21/565 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/3025

摘要： An electronic package is provided, in which an electronic component and conductors are disposed on a substrate structure, and the electronic component and the conductors are covered by an encapsulation layer. A conductive layer is formed on side surfaces of the encapsulation layer and in contact with the conductors, where the conductors are bonding wires used in a wire bonding process. Therefore, a conventional heat sink is replaced by the conductors, thereby reducing a use area of the substrate structure.

公开(公告)号：US20240234328A9

公开(公告)日：2024-07-11

申请号：US18112590

申请日：2023-02-22

申请人： Institute of Semiconductors, Guangdong Academy of Sciences

发明人： Yingqiang YAN ,  Chuan HU ,  Yao WANG ,  Wei ZHENG ,  Zhitao CHEN

IPC分类号： H01L23/538 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065

CPC分类号： H01L23/5389 ,  H01L21/561 ,  H01L21/568 ,  H01L24/24 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/96 ,  H01L25/0652 ,  H01L2224/24137 ,  H01L2224/24141 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/821 ,  H01L2224/95001 ,  H01L2224/96

摘要： A multi-chip interconnection package structure with a heat dissipation plate and a preparation method thereof are provided. The multi-chip interconnection package structure with a heat dissipation plate includes a fine circuit layer, at least one die, a heat dissipation plate, a plastic package body, and a package circuit layer, the heat dissipation plate is provided on the fine circuit layer, and is mounted on a side of the die away from the fine circuit layer, the plastic package body wraps the die and the heat dissipation plate, and the package circuit layer is provided on the plastic package body.

公开(公告)号：US20240234210A1

公开(公告)日：2024-07-11

申请号：US18151643

申请日：2023-01-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jen-Chun Liao ,  Yen-Hung Chen ,  Ching-Hua Hsieh ,  Sung-Yueh Wu ,  Chih-Wei Lin ,  Kung-Chen Yeh

IPC分类号： H01L21/822 ,  H01L21/3065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

CPC分类号： H01L21/822 ,  H01L21/3065 ,  H01L21/56 ,  H01L23/3121 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/80 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0652 ,  H01L2224/08059 ,  H01L2224/08145 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/95001 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/10156 ,  H01L2924/10157

摘要： An integrated circuit package including integrated circuit dies and a method of forming are provided. The integrated circuit package may include a first integrated circuit die and a second integrated circuit die bonded to the first integrated circuit die. The first integrated circuit die may include a first substrate, a first interconnect structure, and a first bonding layer. The first interconnect structure may be between the first bonding layer and the first substrate. The second integrated circuit die may include a second substrate, a second interconnect structure, and a second bonding layer. The second interconnect structure may be between the second bonding layer and the second substrate. A first surface of the first bonding layer may be in direct contact with a first surface of the second bonding layer. A sidewall the first bonding layer and the first surface of the second bonding layer may form a first acute angle.

公开(公告)号：US12033983B2

公开(公告)日：2024-07-09

申请号：US18196905

申请日：2023-05-12

申请人： Intel Corporation

发明人： Junfeng Zhao

IPC分类号： H01L25/065 ,  H01L21/50 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00

CPC分类号： H01L25/0657 ,  H01L24/19 ,  H01L24/96 ,  H01L25/00 ,  H01L25/50 ,  H01L21/50 ,  H01L21/565 ,  H01L23/49816 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73217 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/92144 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48145 ,  H01L2924/00012

摘要： A method for making a semiconductor device includes forming rims on first and second dice. The rims extend laterally away from the first and second dice. The second die is stacked over the first die, and one or more vias are drilled through the rims after stacking. The semiconductor device includes redistribution layers extending over at least one of the respective first and second dice and the corresponding rims. The one or more vias extend through the corresponding rims, and the one or more vias are in communication with the first and second dice through the rims.

公开(公告)号：US12033910B2

公开(公告)日：2024-07-09

申请号：US17028329

申请日：2020-09-22

申请人： Amkor Technology Singapore Holding Pte. Ltd.

发明人： Yeong Beom Ko ,  Dong Jin Kim ,  Se Woong Cha

IPC分类号： H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538

CPC分类号： H01L23/3185 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/92124 ,  H01L2224/92242 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/1434 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2224/94 ,  H01L2224/81 ,  H01L2224/94 ,  H01L2224/82 ,  H01L2224/97 ,  H01L2224/82 ,  H01L2224/97 ,  H01L2224/81 ,  H01L2224/97 ,  H01L2224/83 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012

摘要： A semiconductor product in the form of a stack chip package and a method of manufacturing the same, where a plurality of semiconductor chips are stacked one on another so as to enable the exchange of electrical signals between the semiconductor chips, and where a conductive layer is included for inputting and outputting signals to and from individual chips. A stack chip package having a compact size may, for example, be manufactured by stacking, on a first semiconductor chip, a second semiconductor chip having a smaller surface area by means of interconnection structures so as to enable the exchange of electrical signals between the first and second semiconductor chips, and by using a conductive layer for inputting and outputting signals to and from individual semiconductor chips, in lieu of a thick substrate. Furthermore, heat dissipation effects can be enhanced by the addition of a heat dissipation unit.

公开(公告)号：US20240213171A1

公开(公告)日：2024-06-27

申请号：US18596488

申请日：2024-03-05

申请人： Intel Corporation

发明人： Tomita YOSHIHIRO ,  Eric J. LI ,  Shawna M. LIFF ,  Javier A. FALCON ,  Joshua D. HEPPNER

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/13 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/552 ,  H01L25/04 ,  H01L25/065 ,  H01L25/07 ,  H01L25/075 ,  H01L25/11 ,  H01L25/16

CPC分类号： H01L23/5389 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/48 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/552 ,  H01L24/19 ,  H01L24/48 ,  H01L24/96 ,  H01L25/04 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/16 ,  H01L24/16 ,  H01L25/042 ,  H01L25/071 ,  H01L25/072 ,  H01L25/0753 ,  H01L25/112 ,  H01L25/115 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/81024 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/1203 ,  H01L2924/1304 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/181 ,  H01L2924/1815

摘要： Embodiments of the invention include molded modules and methods for forming molded modules. According to an embodiment the molded modules may be integrated into an electrical package. Electrical packages according to embodiments of the invention may include a die with a redistribution layer formed on at least one surface. The molded module may be mounted to the die. According to an embodiment, the molded module may include a mold layer and a plurality of components encapsulated within the mold layer. Terminals from each of the components may be substantially coplanar with a surface of the mold layer in order to allow the terminals to be electrically coupled to the redistribution layer on the die. Additional embodiments of the invention may include one or more through mold vias formed in the mold layer to provide power delivery and/or one or more faraday cages around components.

公开(公告)号：US12021065B2

公开(公告)日：2024-06-25

申请号：US17498577

申请日：2021-10-11

申请人： Qorvo US, Inc.

发明人： John Robert Siomkos ,  Edward T. Spears ,  Mark Crandall

IPC分类号： H01L25/065 ,  H01L21/3105 ,  H01L21/311 ,  H01L23/00 ,  H01L23/28 ,  H01L23/552 ,  H01L23/66 ,  H01L25/04 ,  H01L25/16 ,  H01L31/0203

CPC分类号： H01L25/0657 ,  H01L21/3105 ,  H01L21/31056 ,  H01L21/311 ,  H01L23/28 ,  H01L23/552 ,  H01L23/66 ,  H01L24/96 ,  H01L24/97 ,  H01L25/043 ,  H01L25/165 ,  H01L31/0203

摘要： The present disclosure relates to a double-sided integrated circuit (IC) module, which includes an exposed semiconductor die on a bottom side. A double-sided IC module includes a module substrate with a top side and a bottom side. Electronic components are mounted to each of the top side and the bottom side. Generally, the electronic components are encapsulated by a mold compound. In an exemplary aspect, a portion of the mold compound on the bottom side of the module substrate is removed, exposing a semiconductor die surface of at least one of the electronic components.