公开(公告)号：US20230326893A1

公开(公告)日：2023-10-12

申请号：US17984446

申请日：2022-11-10

申请人： Samsung Electronics Co., Ltd.

发明人： Sangho CHA ,  Wonjung JANG

IPC分类号： H01L23/00 ,  H01L23/48 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56

CPC分类号： H01L24/13 ,  H01L24/05 ,  H01L23/481 ,  H01L23/3128 ,  H01L23/49822 ,  H01L21/568 ,  H01L2224/0401 ,  H01L2224/02205 ,  H01L2224/02215 ,  H01L2224/05624 ,  H01L2224/13007 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13118 ,  H01L2224/13116

摘要： Disclosed are semiconductor devices and their fabrication methods. The semiconductor device comprises a pad on a semiconductor chip, a protective layer on the semiconductor chip and having an opening that exposes a portion of a top surface of the pad, and a bump structure electrically connected to the pad. The bump structure includes a metal layer on the pad and a solder ball on the metal layer. A first width of the metal layer is about 0.85 times to about 0.95 times a second width of the opening.

公开(公告)号：US11676924B2

公开(公告)日：2023-06-13

申请号：US17195046

申请日：2021-03-08

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Priyal Shah ,  Milind S. Bhagavat ,  Lei Fu

IPC分类号： H01L23/00

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L2224/10145 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13007 ,  H01L2224/13014 ,  H01L2224/13026 ,  H01L2224/13084 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/13172 ,  H01L2224/13181 ,  H01L2224/13184 ,  H01L2924/014 ,  H01L2924/381

摘要： Various semiconductor chips and packages are disclosed. In one aspect, an apparatus is provided that includes a semiconductor chip that has a side, and plural conductive pillars on the side. Each of the conductive pillars includes a pillar portion that has an exposed shoulder facing away from the semiconductor chip. The shoulder provides a wetting surface to attract melted solder. The pillar portion has a first lateral dimension at the shoulder. A solder cap is positioned on the pillar portion. The solder cap has a second lateral dimension smaller than the first lateral dimension.

公开(公告)号：US20190198474A1

公开(公告)日：2019-06-27

申请号：US15498613

申请日：2017-04-27

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： David W. Abraham ,  John M. Cotte

IPC分类号： H01L23/00

CPC分类号： H01L24/17 ,  H01L23/50 ,  H01L24/05 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05572 ,  H01L2224/05666 ,  H01L2224/061 ,  H01L2224/1141 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13006 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/1403 ,  H01L2224/14104 ,  H01L2224/14517 ,  H01L2224/13005 ,  H01L2924/207 ,  H01L2924/00014 ,  H01L2924/013 ,  H01L2924/00012 ,  H01L2224/114 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/01082

摘要： A semiconductor structure and methods for the creation of solder bumps configured to carry a signal and solder bumps configured for ground planes and/or mechanical connections as well as methods for increasing reliability of a chip package generally include formation of multiple sized bump bonds on under bump metallization patterns and/or pads of the same dimension. The signal carrying solder bumps are larger in terms of diameter and bump height than solder bumps configured for ground plane and/or mechanical connections.

公开(公告)号：US20180204831A1

公开(公告)日：2018-07-19

申请号：US15743996

申请日：2015-09-14

申请人： Intel IP Corporation

发明人： Georg SEIDEMANN ,  Christian GEISSLER ,  Klaus REINGRUBER

IPC分类号： H01L27/02 ,  H01L23/00 ,  H01L23/48 ,  H01L25/065 ,  H01L25/18

CPC分类号： H01L27/0296 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/60 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/18 ,  H01L27/0255 ,  H01L28/00 ,  H01L2224/02166 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/12105 ,  H01L2224/13007 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/24137 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48108 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48157 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81815 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/19107 ,  H01L2924/014 ,  H01L2224/45099

摘要： An apparatus including an electrostatic discharge circuit including a first circuit portion coupled beneath a die contact pad of an integrated circuit die and a second circuit portion in an interposer separate from the integrated circuit die, the interposer including a first contact point coupled to the contact pad of the integrated circuit die and a second contact point operable for connection to an external source. A method including forming an integrated circuit die including a first electrostatic discharge structure beneath a contact pad of the die; and coupling the die to an interposer including an interposer contact and a second electrostatic discharge structure, wherein a signal at the contact pad of the die is operable to be routed through the interposer.

公开(公告)号：US20180182725A1

公开(公告)日：2018-06-28

申请号：US15852935

申请日：2017-12-22

申请人： LAPIS Semiconductor Co., Ltd.

发明人： Masanori SHINDO

IPC分类号： H01L23/00

CPC分类号： H01L24/13 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/02206 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05655 ,  H01L2224/11013 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/13007 ,  H01L2224/13021 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2924/01047

摘要： A semiconductor device includes a semiconductor substrate, a conductor provided on a main surface of the semiconductor substrate, an insulating layer disposed to cover a surface of the conductor and having a recess from a surface thereof towards the conductor, the recess having an opening provided at a bottom portion of the recess and exposing a portion of the conductor, and an external connection terminal connected to the portion of the conductor exposed from the opening. In a plan view of the semiconductor device, the external connection terminal covers the entire opening, and the entire external connection terminal is within the recess.

公开(公告)号：US20180151526A1

公开(公告)日：2018-05-31

申请号：US15871586

申请日：2018-01-15

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Michael J. SEDDON ,  Takashi NOMA ,  Kazuhiro SAITO

IPC分类号： H01L23/00 ,  H01L21/48 ,  B23K3/06

CPC分类号： H01L24/11 ,  B23K3/0623 ,  H01L21/4853 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/742 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03828 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/11002 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13007 ,  H01L2224/13026 ,  H01L2224/16227 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/351 ,  H01L2224/03 ,  H01L2224/11

摘要： A semiconductor wafer has an edge support ring around a perimeter of the semiconductor wafer and conductive layer formed over a surface of the semiconductor wafer within the edge support ring. A first stencil is disposed over the edge support ring with first openings aligned with the conductive layer. The first stencil includes a horizontal portion over the edge support ring, and a step-down portion extending the first openings to the conductive layer formed over the surface of the semiconductor wafer. The horizontal portion may have a notch with the edge support ring disposed within the notch. A plurality of bumps is dispersed over the first stencil to occupy the first openings over the conductive layer. A second stencil is disposed over the edge support ring with second openings aligned with the conductive layer to deposit a flux material in the second openings over the conductive layer.

公开(公告)号：US20180114769A1

公开(公告)日：2018-04-26

申请号：US15792767

申请日：2017-10-25

申请人： Sitronix Technology Corp.

发明人： Ying-Chen Chang ,  Po-Chi Chen ,  Kuo-Wei Tseng

IPC分类号： H01L23/00 ,  H01L21/56

CPC分类号： H01L24/81 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/4985 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/13007 ,  H01L2224/13013 ,  H01L2224/13019 ,  H01L2224/13021 ,  H01L2224/13144 ,  H01L2224/16013 ,  H01L2224/16014 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/16502 ,  H01L2224/73253 ,  H01L2224/81097 ,  H01L2224/81193 ,  H01L2224/81345 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81805 ,  H01L2924/00014

摘要： A chip packaging structure includes a chip and a film substrate. The chip is formed with a gold bump, and the film substrate is formed with an inner lead, wherein the gold bump includes a first bonding surface and a plurality of side walls. The gold bump is electrically connected to the inner lead through a eutectic material coverage layer, and the first bonding surface and at least one of the plurality of side walls are covered by the eutectic material coverage layer.

公开(公告)号：US20180083143A1

公开(公告)日：2018-03-22

申请号：US15561996

申请日：2016-03-31

申请人： HAMAMATSU PHOTONICS K.K.

发明人： Noburo HOSOKAWA ,  Nao INOUE ,  Katsumi SHIBAYAMA

IPC分类号： H01L31/02 ,  H01L31/0216 ,  H01L23/00

CPC分类号： H01L27/14687 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/522 ,  H01L23/532 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/14643 ,  H01L31/02005 ,  H01L31/0203 ,  H01L31/02161 ,  H01L31/022408 ,  H01L31/103 ,  H01L31/107 ,  H01L2224/02313 ,  H01L2224/0233 ,  H01L2224/0235 ,  H01L2224/0236 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/02381 ,  H01L2224/0345 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/10126 ,  H01L2224/11 ,  H01L2224/12105 ,  H01L2224/13007 ,  H01L2224/13009 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2924/10253 ,  H01L2924/12043 ,  H01L2924/351 ,  H01L2924/00014

摘要： A semiconductor device includes a semiconductor substrate in which a through hole is formed, a first wiring, an insulating layer, and a second wiring that is electrically connected to the first wiring in an opening of the insulating layer. The insulating layer has a first curved portion that covers an inner surface of a through hole between a first opening and a second opening and a second curved portion that covers an edge of the second opening. A surface in the first curved portion is curved in a convex shape toward the side opposite the inner surface of the through hole. The surface in the second curved portion is curved in a convex shape toward the side opposite the inner surface of the through hole.

公开(公告)号：US09899286B2

公开(公告)日：2018-02-20

申请号：US15153433

申请日：2016-05-12

申请人： STATS ChipPAC Pte. Ltd.

发明人： Rajendra D. Pendse

IPC分类号： H01L21/44 ,  H01L23/48 ,  H01L23/31 ,  H01L21/56 ,  H01L23/498 ,  H01L25/065 ,  H01L21/768 ,  H01L21/78 ,  H01L23/00 ,  H01L33/62

CPC分类号： H01L23/3128 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L21/566 ,  H01L21/76838 ,  H01L21/78 ,  H01L23/3178 ,  H01L23/49838 ,  H01L24/02 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/75 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/0657 ,  H01L33/62 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/0558 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1131 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11823 ,  H01L2224/13007 ,  H01L2224/13016 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13609 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/75 ,  H01L2224/81011 ,  H01L2224/81024 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81208 ,  H01L2224/81801 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2224/97 ,  H01L2225/06558 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/81 ,  H01L2224/13099 ,  H01L2924/01046 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device has a semiconductor die with a die bump pad. A substrate has a conductive trace with an interconnect site. A conductive bump material is deposited on the interconnect site or die bump pad. The semiconductor die is mounted over the substrate so that the bump material is disposed between the die bump pad and interconnect site. The bump material is reflowed without a solder mask around the die bump pad or interconnect site to form an interconnect structure between the die and substrate. The bump material is self-confined within the die bump pad or interconnect site. The volume of bump material is selected so that a surface tension maintains self-confinement of the bump material substantially within a footprint of the die bump pad and interconnect site. The interconnect structure can have a fusible portion and non-fusible portion.

公开(公告)号：US09865555B2

公开(公告)日：2018-01-09

申请号：US15454230

申请日：2017-03-09

申请人： Texas Instruments Incorporated

发明人： Manoj K. Jain

IPC分类号： H01L23/52 ,  H01L23/00 ,  H01L23/528

CPC分类号： H01L24/05 ,  H01L23/528 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0361 ,  H01L2224/03614 ,  H01L2224/03616 ,  H01L2224/03622 ,  H01L2224/03901 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05026 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05172 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05547 ,  H01L2224/05557 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05671 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/13007 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13023 ,  H01L2224/13105 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/81815 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/3651 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/01029

摘要： An integrated circuit including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, with a solder ball formed on the self-aligned under bump metal pad. Processes of forming integrated circuits including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, by a process of forming one or more metal layers on the interconnect level and the dielectric layer, selectively removing the metal from over the dielectric layer, and subsequently forming a solder ball on the self-aligned under bump metal pad. Some examples include additional metal layers formed after the selective removal process, and may include an additional selective removal process on the additional metal layers.