公开(公告)号：US09491840B2

公开(公告)日：2016-11-08

申请号：US14026060

申请日：2013-09-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wen-Chien Chang ,  Hsiang-Tai Lu ,  Dai-Jang Chen ,  Chih-Hsien Lin

IPC: H01L21/00 ,  H05F3/02 ,  H01L21/67 ,  H01L23/60 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L24/75 ,  H01L21/67207 ,  H01L23/49827 ,  H01L23/60 ,  H01L24/03 ,  H01L24/04 ,  H01L24/11 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0346 ,  H01L2224/0361 ,  H01L2224/0362 ,  H01L2224/038 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/75101 ,  H01L2224/752 ,  H01L2224/81009 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/30205 ,  H05F3/02 ,  Y10T29/52 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/207 ,  H01L2924/01029 ,  H01L2924/01047

Abstract: In a process, at least one circuit element is formed in a substrate. A conductive layer is formed over the substrate and in electrical contact with the at least one circuit element. Electrostatic charges are discharged from the substrate via the conductive layer.

Abstract translation: 在一个过程中，在衬底中形成至少一个电路元件。 导电层形成在衬底上并与至少一个电路元件电接触。 静电电荷经由导电层从基板排出。

公开(公告)号：US11335672B2

公开(公告)日：2022-05-17

申请号：US16937343

申请日：2020-07-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Hsiang-Tai Lu ,  Shuo-Mao Chen ,  Mill-Jer Wang ,  Feng-Cheng Hsu ,  Chao-Hsiang Yang ,  Shin-Puu Jeng ,  Cheng-Yi Hong ,  Chih-Hsien Lin ,  Dai-Jang Chen ,  Chen-Hua Lin

IPC: H01L25/00 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L21/66 ,  H01L23/498 ,  H01L23/522 ,  H01L23/053

Abstract: A method of manufacturing a semiconductor structure forming a redistribution layer (RDL); forming a conductive pad over the RDL; performing a first electrical test through the conductive pad; bonding a first die over the RDL by a connector; disposing a first underfill material to surround the connector; performing a second electrical test through the conductive pad; disposing a second die over the first die and the conductive pad; and disposing a second underfill material to surround the second die, wherein the conductive pad is at least partially in contact with the second underfill material, and is protruded from the RDL during the first electrical test and the second electrical test.

公开(公告)号：US10269586B2

公开(公告)日：2019-04-23

申请号：US14621567

申请日：2015-02-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Bruce C. S. Chou ,  Chih-Hsien Lin ,  Hsiang-Tai Lu ,  Jung-Kuo Tu ,  Tung-Hung Hsieh ,  Chen-Hua Lin ,  Mingo Liu

IPC: H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/538 ,  H01L21/48 ,  H01L21/768 ,  H01L23/31 ,  H01L23/14 ,  H01L23/498

Abstract: A semiconductor device includes a first die having a first active surface and a first backside surface opposite the first active surface, a second die having a second active surface and a second backside surface opposite the second active surface, and an interposer, the first active surface of the first die being electrically coupled to a first side of the interposer, the second active surface of the second die being electrically coupled to a second side of the interposer. The semiconductor device also includes a first connector over the interposer, a first encapsulating material surrounding the second die, the first encapsulating material having a first surface over the interposer, and a via electrically coupling the first connector and the interposer. A first end of the via is substantially coplanar with the first surface of the first encapsulating material.

公开(公告)号：US09209048B2

公开(公告)日：2015-12-08

申请号：US14276832

申请日：2014-05-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wen-Chun Huang ,  Chien-Chen Li ,  Kuo-Chio Liu ,  Ruey-Yun Shiue ,  Hsi-Kuei Cheng ,  Chih-Hsien Lin ,  Jing-Cheng Lin ,  Hsiang-Tai Lu ,  Tzi-Yi Shieh

IPC: H01L21/56 ,  H01L23/28 ,  H01L23/29 ,  H01L23/31 ,  H01L23/60 ,  H01L25/065

CPC classification number: H01L21/565 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/145 ,  H01L23/147 ,  H01L23/28 ,  H01L23/29 ,  H01L23/31 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5329 ,  H01L23/5384 ,  H01L23/60 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/05583 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/11002 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/13082 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/81895 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10254 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/10333 ,  H01L2924/10335 ,  H01L2924/10342 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00012

Abstract: Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a method including mounting a die to a top surface of a substrate to form a device, encapsulating the die and top surface of the substrate in a mold compound, the mold compound having a first thickness over the die, and removing a portion, but not all, of the thickness of the mold compound over the die. The method further includes performing further processing on the device, and removing the remaining thickness of the mold compound over the die.

Abstract translation: 本公开的实施例包括半导体封装及其形成方法。 一个实施例是一种方法，包括将管芯安装到衬底的顶表面以形成器件，将衬底的管芯和顶表面封装在模具化合物中，模具化合物在模具上具有第一厚度，并且去除部分 但不是全部，模具上的模具化合物的厚度。 所述方法还包括对所述装置执行进一步的处理，以及去除所述模具上的所述模制化合物的剩余厚度。

公开(公告)号：US20150187607A1

公开(公告)日：2015-07-02

申请号：US14276832

申请日：2014-05-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wen-Chun Huang ,  Chien-Chen Li ,  Kuo-Chio Liu ,  Ruey-Yun Shiue ,  Hsi-Kuei Cheng ,  Chih-Hsien Lin ,  Jing-Cheng Lin ,  Hsiang-Tai Lu ,  Tzi-Yi Shieh

IPC: H01L21/56 ,  H01L25/065 ,  H01L23/60 ,  H01L23/29 ,  H01L23/31

CPC classification number: H01L21/565 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/145 ,  H01L23/147 ,  H01L23/28 ,  H01L23/29 ,  H01L23/31 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5329 ,  H01L23/5384 ,  H01L23/60 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/05583 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/11002 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/13082 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/81895 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10254 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/10333 ,  H01L2924/10335 ,  H01L2924/10342 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00012

Abstract: Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a method including mounting a die to a top surface of a substrate to form a device, encapsulating the die and top surface of the substrate in a mold compound, the mold compound having a first thickness over the die, and removing a portion, but not all, of the thickness of the mold compound over the die. The method further includes performing further processing on the device, and removing the remaining thickness of the mold compound over the die.

Abstract translation: 本公开的实施例包括半导体封装及其形成方法。 一个实施例是一种方法，包括将管芯安装到衬底的顶表面以形成器件，将衬底的管芯和顶表面封装在模具化合物中，模具化合物在模具上具有第一厚度，并且去除部分 但不是全部，模具上的模具化合物的厚度。 所述方法还包括对所述装置执行进一步的处理，以及去除所述模具上的所述模制化合物的剩余厚度。

公开(公告)号：US20150162220A1

公开(公告)日：2015-06-11

申请号：US14621567

申请日：2015-02-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Bruce C.S. Chou ,  Chih-Hsien Lin ,  Hsiang-Tai Lu ,  Jung-Kuo Tu ,  Tung-Hung Hsieh ,  Chen-Hua Lin ,  Mingo Liu

IPC: H01L21/56 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L21/56 ,  H01L21/486 ,  H01L21/563 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/3135 ,  H01L23/3185 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/2101 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81193 ,  H01L2224/81424 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/81895 ,  H01L2224/82101 ,  H01L2224/83104 ,  H01L2224/85 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/1531 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2924/014 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01074 ,  H01L2924/01028 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A semiconductor device includes a first die having a first active surface and a first backside surface opposite the first active surface, a second die having a second active surface and a second backside surface opposite the second active surface, and an interposer, the first active surface of the first die being electrically coupled to a first side of the interposer, the second active surface of the second die being electrically coupled to a second side of the interposer. The semiconductor device also includes a first connector over the interposer, a first encapsulating material surrounding the second die, the first encapsulating material having a first surface over the interposer, and a via electrically coupling the first connector and the interposer. A first end of the via is substantially coplanar with the first surface of the first encapsulating material.

Abstract translation: 半导体器件包括具有第一有源表面和与第一有源表面相对的第一背面的第一管芯，具有第二有源表面和与第二有源表面相对的第二背面的第二管芯，以及插入件，第一有源表面 所述第一管芯电耦合到所述插入件的第一侧，所述第二管芯的所述第二有源表面电连接到所述插入件的第二侧。 半导体器件还包括位于插入器上的第一连接器，围绕第二管芯的第一封装材料，第一封装材料具有位于插入件上的第一表面，以及电连接第一连接器和插入件的通孔。 通孔的第一端与第一封装材料的第一表面基本共面。

公开(公告)号：US20250054934A1

公开(公告)日：2025-02-13

申请号：US18366327

申请日：2023-08-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wei-Yu Chou ,  Yang-Che Chen ,  Yi-Lun Yang ,  Ting-Yuan Huang ,  Hsiang-Tai Lu

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L23/528 ,  H01L25/00

Abstract: An integrated circuit (IC) package includes a first integrated circuit (IC) device. An interconnection structure is disposed over the first IC device in a cross-sectional side view. The interconnection structure includes a plurality of interconnection components. A cavity is disposed in the interconnection structure in the cross-sectional side view. A second IC device is disposed at least partially within the cavity in the cross-sectional side view. The second IC device is electrically coupled to the first IC device through at least a subset of the interconnection components of the interconnection structure. A non-metallic material partially fills the cavity. The second IC device is at least partially surrounded by the non-metallic material in the cross-sectional side view and in a top view.

公开(公告)号：US20240387411A1

公开(公告)日：2024-11-21

申请号：US18789106

申请日：2024-07-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Hsuan Tai ,  Ming-Chung Wu ,  Kuo-Wen Chen ,  Hsiang-Tai Lu

IPC: H01L23/58 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528

Abstract: Semiconductor structures and methods of testing the same are provided. A semiconductor structure according to the present disclosure includes a substrate, a semiconductor device over the substrate, wherein the semiconductor device includes an interconnect structure, and the interconnect structure includes a plurality of metallization layers disposed in a dielectric layer; and a delamination sensor. The delamination sensor includes a connecting structure and a plurality of contact vias in at least one of the plurality of metallization layers. The connecting structure bonds the semiconductor device to the substrate and does not functionally couple the semiconductor device to the substrate. The plurality of contact vias fall within a first region of a vertical projection area of the connecting structure but do not overlap a second region of the vertical projection area.

公开(公告)号：US11855066B2

公开(公告)日：2023-12-26

申请号：US17743455

申请日：2022-05-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Hsiang-Tai Lu ,  Shuo-Mao Chen ,  Mill-Jer Wang ,  Feng-Cheng Hsu ,  Chao-Hsiang Yang ,  Shin-Puu Jeng ,  Cheng-Yi Hong ,  Chih-Hsien Lin ,  Dai-Jang Chen ,  Chen-Hua Lin

IPC: H01L25/00 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L21/66 ,  H01L23/498 ,  H01L23/522 ,  H01L23/053

CPC classification number: H01L25/50 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/565 ,  H01L22/20 ,  H01L22/32 ,  H01L23/3135 ,  H01L23/3185 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L21/4857 ,  H01L21/563 ,  H01L22/14 ,  H01L23/053 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/23 ,  H01L24/24 ,  H01L2224/02379 ,  H01L2224/16225 ,  H01L2224/214 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/3511 ,  Y02P80/30 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor structure forming a redistribution layer (RDL); forming a conductive pad over the RDL; performing a first electrical test through the conductive pad; bonding a first die over the RDL by a connector; disposing a first underfill material to surround the connector; performing a second electrical test through the conductive pad; disposing a second die over the first die and the conductive pad; and disposing a second underfill material to surround the second die, wherein the conductive pad is at least partially in contact with the second underfill material, and is protruded from the RDL during the first electrical test and the second electrical test.

公开(公告)号：US20220375877A1

公开(公告)日：2022-11-24

申请号：US17365699

申请日：2021-07-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Hsuan Tai ,  Ming-Chung Wu ,  Kuo-Wen Chen ,  Hsiang-Tai Lu

IPC: H01L23/58 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528

Abstract: Semiconductor structures and methods of testing the same are provided. A semiconductor structure according to the present disclosure includes a substrate, a semiconductor device over the substrate, wherein the semiconductor device includes an interconnect structure, and the interconnect structure includes a plurality of metallization layers disposed in a dielectric layer; and a delamination sensor. The delamination sensor includes a connecting structure and a plurality of contact vias in at least one of the plurality of metallization layers. The connecting structure bonds the semiconductor device to the substrate and does not functionally couple the semiconductor device to the substrate. The plurality of contact vias fall within a first region of a vertical projection area of the connecting structure but do not overlap a second region of the vertical projection area.