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公开(公告)号:US11335672B2
公开(公告)日:2022-05-17
申请号:US16937343
申请日:2020-07-23
Inventor: Hsiang-Tai Lu , Shuo-Mao Chen , Mill-Jer Wang , Feng-Cheng Hsu , Chao-Hsiang Yang , Shin-Puu Jeng , Cheng-Yi Hong , Chih-Hsien Lin , Dai-Jang Chen , Chen-Hua Lin
IPC: H01L25/00 , H01L23/538 , H01L23/31 , H01L23/00 , H01L25/10 , H01L21/48 , H01L21/56 , H01L21/66 , H01L23/498 , H01L23/522 , H01L23/053
Abstract: A method of manufacturing a semiconductor structure forming a redistribution layer (RDL); forming a conductive pad over the RDL; performing a first electrical test through the conductive pad; bonding a first die over the RDL by a connector; disposing a first underfill material to surround the connector; performing a second electrical test through the conductive pad; disposing a second die over the first die and the conductive pad; and disposing a second underfill material to surround the second die, wherein the conductive pad is at least partially in contact with the second underfill material, and is protruded from the RDL during the first electrical test and the second electrical test.
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公开(公告)号:US09941239B2
公开(公告)日:2018-04-10
申请号:US15345134
申请日:2016-11-07
Inventor: Wen-Chien Chang , Hsiang-Tai Lu , Dai-Jang Chen , Chih-Hsien Lin
IPC: H01L21/00 , H01L23/00 , H05F3/02 , H01L21/67 , H01L23/60 , H01L25/00 , H01L23/498 , H01L25/065
CPC classification number: H01L24/75 , H01L21/67207 , H01L23/49827 , H01L23/60 , H01L24/03 , H01L24/04 , H01L24/11 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/0346 , H01L2224/0361 , H01L2224/0362 , H01L2224/038 , H01L2224/03912 , H01L2224/0401 , H01L2224/05009 , H01L2224/05022 , H01L2224/05124 , H01L2224/05147 , H01L2224/05572 , H01L2224/0558 , H01L2224/05655 , H01L2224/05666 , H01L2224/1146 , H01L2224/11849 , H01L2224/13005 , H01L2224/13022 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/75101 , H01L2224/752 , H01L2224/81009 , H01L2225/06513 , H01L2225/06541 , H01L2924/1305 , H01L2924/13091 , H01L2924/15787 , H01L2924/15788 , H01L2924/30205 , H05F3/02 , Y10T29/52 , H01L2924/00 , H01L2924/014 , H01L2924/00014 , H01L2924/207 , H01L2924/01029 , H01L2924/01047
Abstract: In a process, at least one circuit element is formed in a substrate. A conductive layer is formed over the substrate and in electrical contact with the at least one circuit element. Electrostatic charges are discharged from the substrate via the conductive layer.
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公开(公告)号:US11855066B2
公开(公告)日:2023-12-26
申请号:US17743455
申请日:2022-05-13
Inventor: Hsiang-Tai Lu , Shuo-Mao Chen , Mill-Jer Wang , Feng-Cheng Hsu , Chao-Hsiang Yang , Shin-Puu Jeng , Cheng-Yi Hong , Chih-Hsien Lin , Dai-Jang Chen , Chen-Hua Lin
IPC: H01L25/00 , H01L23/538 , H01L23/31 , H01L23/00 , H01L25/10 , H01L21/48 , H01L21/56 , H01L21/66 , H01L23/498 , H01L23/522 , H01L23/053
CPC classification number: H01L25/50 , H01L21/486 , H01L21/4853 , H01L21/565 , H01L22/20 , H01L22/32 , H01L23/3135 , H01L23/3185 , H01L23/5386 , H01L24/19 , H01L24/20 , H01L25/105 , H01L21/4857 , H01L21/563 , H01L22/14 , H01L23/053 , H01L23/3128 , H01L23/49827 , H01L23/49838 , H01L23/5226 , H01L23/5383 , H01L23/5384 , H01L23/5389 , H01L23/562 , H01L24/23 , H01L24/24 , H01L2224/02379 , H01L2224/16225 , H01L2224/214 , H01L2224/32225 , H01L2224/73204 , H01L2225/1035 , H01L2225/1058 , H01L2924/15311 , H01L2924/18161 , H01L2924/3511 , Y02P80/30 , H01L2224/73204 , H01L2224/16225 , H01L2224/32225 , H01L2924/00
Abstract: A method of manufacturing a semiconductor structure forming a redistribution layer (RDL); forming a conductive pad over the RDL; performing a first electrical test through the conductive pad; bonding a first die over the RDL by a connector; disposing a first underfill material to surround the connector; performing a second electrical test through the conductive pad; disposing a second die over the first die and the conductive pad; and disposing a second underfill material to surround the second die, wherein the conductive pad is at least partially in contact with the second underfill material, and is protruded from the RDL during the first electrical test and the second electrical test.
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公开(公告)号:US10741537B2
公开(公告)日:2020-08-11
申请号:US15725766
申请日:2017-10-05
Inventor: Hsiang-Tai Lu , Shuo-Mao Chen , Mill-Jer Wang , Feng-Cheng Hsu , Chao-Hsiang Yang , Shin-Puu Jeng , Cheng-Yi Hong , Chih-Hsien Lin , Dai-Jang Chen , Chen-Hua Lin
IPC: H01L25/00 , H01L23/538 , H01L23/31 , H01L23/00 , H01L25/10 , H01L21/48 , H01L21/56 , H01L21/66 , H01L23/498 , H01L23/522 , H01L23/053
Abstract: A method of manufacturing a semiconductor structure includes forming a redistribution layer (RDL); forming a conductive member over the RDL; performing a first electrical test through the conductive member; disposing a first die over the RDL; performing a second electrical test through the conductive member; and disposing a second die over the first die and the conductive member.
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公开(公告)号:US09491840B2
公开(公告)日:2016-11-08
申请号:US14026060
申请日:2013-09-13
Inventor: Wen-Chien Chang , Hsiang-Tai Lu , Dai-Jang Chen , Chih-Hsien Lin
CPC classification number: H01L24/75 , H01L21/67207 , H01L23/49827 , H01L23/60 , H01L24/03 , H01L24/04 , H01L24/11 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/0346 , H01L2224/0361 , H01L2224/0362 , H01L2224/038 , H01L2224/03912 , H01L2224/0401 , H01L2224/05009 , H01L2224/05022 , H01L2224/05124 , H01L2224/05147 , H01L2224/05572 , H01L2224/0558 , H01L2224/05655 , H01L2224/05666 , H01L2224/1146 , H01L2224/11849 , H01L2224/13005 , H01L2224/13022 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/75101 , H01L2224/752 , H01L2224/81009 , H01L2225/06513 , H01L2225/06541 , H01L2924/1305 , H01L2924/13091 , H01L2924/15787 , H01L2924/15788 , H01L2924/30205 , H05F3/02 , Y10T29/52 , H01L2924/00 , H01L2924/014 , H01L2924/00014 , H01L2924/207 , H01L2924/01029 , H01L2924/01047
Abstract: In a process, at least one circuit element is formed in a substrate. A conductive layer is formed over the substrate and in electrical contact with the at least one circuit element. Electrostatic charges are discharged from the substrate via the conductive layer.
Abstract translation: 在一个过程中,在衬底中形成至少一个电路元件。 导电层形成在衬底上并与至少一个电路元件电接触。 静电电荷经由导电层从基板排出。
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