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    Method of shielding through silicon vias in a passive interposer
    1.
    发明授权
    Method of shielding through silicon vias in a passive interposer 有权
    在无源中介层中通过硅通孔屏蔽的方法

    公开(公告)号：US09159564B2

    公开(公告)日：2015-10-13

    申请号：US14094847

    申请日：2013-12-03

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Hsiang-Tai Lu ,  Chih-Hsien Lin ,  Meng-Lin Chung

    IPC: H01L21/265 ,  H01L23/552 ,  H01L23/14 ,  H01L23/498 ,  H01L21/768 ,  H01L23/522

    CPC classification number: H01L21/265 ,  H01L21/76802 ,  H01L23/147 ,  H01L23/49827 ,  H01L23/5225 ,  H01L23/552 ,  H01L2224/16

    Abstract: A method of shielding through silicon vias (TSVs) in a passive interposer includes doping a substrate with positive ions, and implanting positive ions in an upper portion of the substrate, such that the substrate has at least a p-doped portion and a heavily p-doped upper portion. The method further includes forming an interlayer dielectric (ILD) above the heavily p-doped upper portion. The method further includes forming a plurality of through silicon vias (TSVs) through the ILD and the substrate, such that the passive interposer is configured to electrically couple at least one structure above and below the passive interposer. The method further includes forming, between pairs of TSVs of the plurality of TSVs, a plurality of shielding lines through the interlayer dielectric, the shielding lines configured to electrically couple the heavily p-doped upper portion of the substrate and at least one interconnect structure above the ILD.

    Abstract translation: 在无源插入器中通过硅通孔（TSV）屏蔽的方法包括用正离子掺杂衬底，并在衬底的上部注入正离子，使得衬底至少具有p掺杂部分和大量p 掺杂上部。 该方法还包括在高p掺杂的上部部分上形成层间电介质（ILD）。 该方法还包括通过ILD和衬底形成多个穿通硅通孔（TSV），使得被动中插入口被配置为电耦合无源插入器的上方和下方的至少一个结构。 所述方法还包括在所述多个TSV的TSV对之间形成穿过所述层间电介质的多条屏蔽线，所述屏蔽线被配置为电耦合所述衬底的所述p掺杂的高部分和至少一个互连结构 ILD。

    Delamination sensor
    3.
    发明授权
    Delamination sensor 有权

    公开(公告)号：US12125810B2

    公开(公告)日：2024-10-22

    申请号：US18190361

    申请日：2023-03-27

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Chih-Hsuan Tai ,  Ming-Chung Wu ,  Kuo-Wen Chen ,  Hsiang-Tai Lu

    IPC: H01L23/58 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528

    CPC classification number: H01L23/585 ,  H01L23/49816 ,  H01L23/5226 ,  H01L23/528

    Abstract: Semiconductor structures and methods of testing the same are provided. A semiconductor structure according to the present disclosure includes a substrate, a semiconductor device over the substrate, wherein the semiconductor device includes an interconnect structure, and the interconnect structure includes a plurality of metallization layers disposed in a dielectric layer; and a delamination sensor. The delamination sensor includes a connecting structure and a plurality of contact vias in at least one of the plurality of metallization layers. The connecting structure bonds the semiconductor device to the substrate and does not functionally couple the semiconductor device to the substrate. The plurality of contact vias fall within a first region of a vertical projection area of the connecting structure but do not overlap a second region of the vertical projection area.

    DELAMINATION SENSOR
    4.
    发明公开
    DELAMINATION SENSOR 审中-公开

    公开(公告)号：US20230238340A1

    公开(公告)日：2023-07-27

    申请号：US18190361

    申请日：2023-03-27

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Chih-Hsuan Tai ,  Ming-Chung Wu ,  Kuo-Wen Chen ,  Hsiang-Tai Lu

    IPC: H01L23/58 ,  H01L23/528 ,  H01L23/522 ,  H01L23/498

    CPC classification number: H01L23/585 ,  H01L23/528 ,  H01L23/5226 ,  H01L23/49816

    Abstract: Semiconductor structures and methods of testing the same are provided. A semiconductor structure according to the present disclosure includes a substrate, a semiconductor device over the substrate, wherein the semiconductor device includes an interconnect structure, and the interconnect structure includes a plurality of metallization layers disposed in a dielectric layer; and a delamination sensor. The delamination sensor includes a connecting structure and a plurality of contact vias in at least one of the plurality of metallization layers. The connecting structure bonds the semiconductor device to the substrate and does not functionally couple the semiconductor device to the substrate. The plurality of contact vias fall within a first region of a vertical projection area of the connecting structure but do not overlap a second region of the vertical projection area.

    Delamination sensor
    5.
    发明授权
    Delamination sensor 有权

    公开(公告)号：US11616029B2

    公开(公告)日：2023-03-28

    申请号：US17365699

    申请日：2021-07-01

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Chih-Hsuan Tai ,  Ming-Chung Wu ,  Kuo-Wen Chen ,  Hsiang-Tai Lu

    IPC: H01L23/58 ,  H01L23/528 ,  H01L23/522 ,  H01L23/498

    Abstract: Semiconductor structures and methods of testing the same are provided. A semiconductor structure according to the present disclosure includes a substrate, a semiconductor device over the substrate, wherein the semiconductor device includes an interconnect structure, and the interconnect structure includes a plurality of metallization layers disposed in a dielectric layer; and a delamination sensor. The delamination sensor includes a connecting structure and a plurality of contact vias in at least one of the plurality of metallization layers. The connecting structure bonds the semiconductor device to the substrate and does not functionally couple the semiconductor device to the substrate. The plurality of contact vias fall within a first region of a vertical projection area of the connecting structure but do not overlap a second region of the vertical projection area.

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