公开(公告)号：US06256875B1

公开(公告)日：2001-07-10

申请号：US09400912

申请日：1999-09-22

Applicant: Masaki Watanabe ,  Akiyoshi Sawai ,  Yoshikazu Narutaki ,  Tomoaki Hashimoto ,  Masatoshi Yasunaga ,  Jun Shibata ,  Hiroshi Seki ,  Kazuhiko Kurafuchi ,  Katsunori Asai

Inventor： Masaki Watanabe ,  Akiyoshi Sawai ,  Yoshikazu Narutaki ,  Tomoaki Hashimoto ,  Masatoshi Yasunaga ,  Jun Shibata ,  Hiroshi Seki ,  Kazuhiko Kurafuchi ,  Katsunori Asai

IPC: H05K336

CPC classification number: H01L24/49 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/3675 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/48 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/3025 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: The minimum spacing between wires disposed on a printed circuit board of a printed circuit board ball grid array package is reduced. Wiring layers are narrower than in the prior art because they are not plated and because only one metal layer is plated on the wiring layers. The narrower wiring layers can be formed easily with small spaces between wires.

Abstract translation: 设置在印刷电路板球栅阵列封装的印刷电路板上的布线之间的最小间距减小。 接线层比现有技术更窄，因为它们不被电镀，并且因为在布线层上仅镀一个金属层。 可以容易地形成较窄的布线层，导线之间的间隔较小。

公开(公告)号：US06191493B1

公开(公告)日：2001-02-20

申请号：US09260594

申请日：1999-03-02

Applicant: Masatoshi Yasunaga ,  Shin Nakao ,  Shinji Baba ,  Mitsuyasu Matsuo ,  Hironori Matsushima

Inventor： Masatoshi Yasunaga ,  Shin Nakao ,  Shinji Baba ,  Mitsuyasu Matsuo ,  Hironori Matsushima

IPC: H01L2144

CPC classification number: H01L21/568 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/3107 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/81 ,  H01L25/10 ,  H01L25/105 ,  H01L2224/0231 ,  H01L2224/0233 ,  H01L2224/02333 ,  H01L2224/02335 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/1131 ,  H01L2224/11332 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/1191 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16105 ,  H01L2224/16108 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/4813 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/812 ,  H01L2224/81801 ,  H01L2224/83104 ,  H01L2225/1005 ,  H01L2225/1035 ,  H01L2225/107 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/351 ,  H05K3/303 ,  H05K3/3442 ,  H05K2201/09909 ,  H05K2201/10454 ,  H05K2201/10484 ,  H05K2201/2036 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Bonding pads are formed on a main surface of a semiconductor chip. An insulating layer having openings located on the bonding pads is formed on the main surface of the semiconductor chip. Base metal layers are formed on the bonding pads. A buffer coat film having a portion laid on a periphery of the base metal layer is formed on the insulating layer. Connection layers are formed on the base metal layers. First conductors are formed on the connection layers. A seal resin exposing only top surfaces of the first conductors is formed. Lumpish second conductors are formed on the top surfaces of the first conductor. Thereby, a resin seal semiconductor package can be made compact and it has improved electrical characteristics and high reliability.

Abstract translation: 接合焊盘形成在半导体芯片的主表面上。 在半导体芯片的主表面上形成具有位于接合焊盘上的开口的绝缘层。 在接合焊盘上形成基底金属层。 在绝缘层上形成具有放置在基底金属层周围的部分的缓冲涂膜。 连接层形成在基底金属层上。 第一导体形成在连接层上。 形成仅露出第一导体的顶表面的密封树脂。 在第一导体的顶表面上形成笨重的第二导体。 因此，可以使树脂密封半导体封装紧凑并且具有改善的电特性和高可靠性。

公开(公告)号：US6005289A

公开(公告)日：1999-12-21

申请号：US738935

申请日：1996-10-24

Applicant: Masaki Watanabe ,  Akiyoshi Sawai ,  Yoshikazu Narutaki ,  Tomoaki Hashimoto ,  Masatoshi Yasunaga ,  Jun Shibata ,  Hiroshi Seki ,  Kazuhiko Kurafuchi ,  Katsunori Asai

Inventor： Masaki Watanabe ,  Akiyoshi Sawai ,  Yoshikazu Narutaki ,  Tomoaki Hashimoto ,  Masatoshi Yasunaga ,  Jun Shibata ,  Hiroshi Seki ,  Kazuhiko Kurafuchi ,  Katsunori Asai

IPC: H05K3/46 ,  H01L21/48 ,  H01L23/12 ,  H01L23/13 ,  H01L23/367 ,  H01L23/498 ,  H01L23/053 ,  H01L23/48

CPC classification number: H01L24/49 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/3675 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49833 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/16195 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/3025 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49165

Abstract: The minimum spacing between wires disposed on a printed circuit board of a printed circuit board ball grid array package is reduced. Wiring layers are narrower than in the prior art because they are not plated and because only one metal layer is plated on the wiring layers. The narrower wiring layers can be formed easily with small spaces between wires.

Abstract translation: 设置在印刷电路板球栅阵列封装的印刷电路板上的布线之间的最小间距减小。 接线层比现有技术更窄，因为它们不被电镀，并且因为在布线层上仅镀一个金属层。 可以容易地形成较窄的布线层，导线之间的间隔较小。

公开(公告)号：US08692383B2

公开(公告)日：2014-04-08

申请号：US13231856

申请日：2011-09-13

Applicant: Soshi Kuroda ,  Kenya Hironaga ,  Hironori Matsushima ,  Masatoshi Yasunaga ,  Akira Yamazaki

Inventor： Soshi Kuroda ,  Kenya Hironaga ,  Hironori Matsushima ,  Masatoshi Yasunaga ,  Akira Yamazaki

IPC: H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC classification number: H01L24/46 ,  H01L21/6836 ,  H01L23/3121 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/743 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/26175 ,  H01L2224/27312 ,  H01L2224/27334 ,  H01L2224/27436 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/83385 ,  H01L2224/838 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/3512

Abstract: To achieve a reduction in cost of a semiconductor device, in a common board (a wiring board), a plurality of bonding leads each extend toward the center of the board, and a solder resist film as a die bonding region supporting a minimum chip is coated with a die bonding material. With this, even when a first semiconductor chip as a large chip is mounted, wire bonding can be performed without causing the die bonding material to cover the bonding leads. Thus, development cost can be reduced to reduce the cost of the semiconductor device (LGA).

Abstract translation: 为了实现半导体器件的成本降低，在公共板（布线板）中，多个接合引线各自朝向基板的中心延伸，并且作为支撑最小芯片的芯片接合区域的阻焊膜为 涂有芯片接合材料。 由此，即使安装作为大芯片的第一半导体芯片，也可以在不使芯片接合材料覆盖接合引线的情况下进行引线接合。 因此，可以降低开发成本以降低半导体器件（LGA）的成本。

公开(公告)号：US08293575B2

公开(公告)日：2012-10-23

申请号：US12834937

申请日：2010-07-13

Applicant: Tatsuya Hirai ,  Tomoaki Hashimoto ,  Takashi Kikuchi ,  Masatoshi Yasunaga ,  Michiaki Sugiyama

Inventor： Tatsuya Hirai ,  Tomoaki Hashimoto ,  Takashi Kikuchi ,  Masatoshi Yasunaga ,  Michiaki Sugiyama

IPC: H01L23/28

CPC classification number: H01L25/50 ,  H01L21/561 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/16 ,  H01L2224/05553 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012

Abstract: The reliability of a semiconductor device is improved. A sealing resin (sealed body) is formed between a sub-substrate (first base member) and a base substrate (second base member) that are provided individually and distinctly to be integrated therewith, and then, the sub-substrate is electrically coupled to the second base member. As a means for electrically coupling the sub-substrate to the base substrate, lands (first lands) formed on the sub-substrate and lands (second lands) formed on the base substrate are disposed such that the respective positions thereof are aligned. After through holes are formed from the lands of the sub-substrate toward the lands of the base substrate, a solder member (conductive member) is formed in each of the through holes.

Abstract translation: 提高了半导体器件的可靠性。 在单独且明显地与其一体化设置的子基板（第一基底构件）和基底基板（第二基底构件）之间形成密封树脂（密封体），然后，将辅助基板电耦合到 第二个基础成员。 作为将基板与基板电连接的装置，在基板上形成的焊盘（第一焊盘）和基板上形成的焊盘（第二焊盘）配置成使其各自的位置对齐。 在从底基板的台阶朝向基板的焊盘形成通孔之后，在每个通孔中形成焊料部件（导电部件）。

公开(公告)号：US20100320623A1

公开(公告)日：2010-12-23

申请号：US12792166

申请日：2010-06-02

Applicant: Soshi Kuroda ,  Masatoshi Yasunaga ,  Hironori Matsushima ,  Kenya Hironaga

Inventor： Soshi Kuroda ,  Masatoshi Yasunaga ,  Hironori Matsushima ,  Kenya Hironaga

IPC: H01L23/52 ,  H01L21/50

CPC classification number: H01L21/565 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/32013 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49171 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A multi-pin semiconductor device with improved reliability. In a multi-pin BGA, a plurality of wires for electrically coupling a semiconductor chip and a wiring substrate include a plurality of short and thin first wires located in an inner position and a plurality of second wires longer and thicker than the first wires. Since resin flows in from between thin first wires during resin molding, the resin pushes out air, thereby suppressing formation of voids. The reliability of the multi-pin BGA is thus improved.

Abstract translation: 一种具有改进可靠性的多针半导体器件。 在多引脚BGA中，用于电耦合半导体芯片和布线基板的多根导线包括位于内部位置的多个短而细的第一布线和比第一布线更长和更厚的多个第二布线。 由于在树脂成型时树脂从薄的第一布线之间流入，所以树脂推出空气，从而抑制空隙的形成。 因此，提高了多引脚BGA的可靠性。

公开(公告)号：US5753973A

公开(公告)日：1998-05-19

申请号：US798954

申请日：1997-02-11

Applicant: Masatoshi Yasunaga ,  Shin Nakao ,  Shinji Baba ,  Mitsuyasu Matsuo ,  Hironori Matsushima

Inventor： Masatoshi Yasunaga ,  Shin Nakao ,  Shinji Baba ,  Mitsuyasu Matsuo ,  Hironori Matsushima

IPC: H01L21/60 ,  H01L21/56 ,  H01L21/68 ,  H01L23/12 ,  H01L23/28 ,  H01L23/31 ,  H01L23/32 ,  H01L23/485 ,  H01L25/10 ,  H05K3/30 ,  H05K3/34 ,  H01L23/48

CPC classification number: H01L21/568 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/3107 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/10 ,  H01L25/105 ,  H05K3/303 ,  H01L2224/0231 ,  H01L2224/0233 ,  H01L2224/02333 ,  H01L2224/02335 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/1131 ,  H01L2224/11332 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/1191 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16105 ,  H01L2224/16108 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/4813 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/812 ,  H01L2224/81801 ,  H01L2224/83104 ,  H01L2225/1005 ,  H01L2225/1035 ,  H01L2225/107 ,  H01L24/45 ,  H01L24/48 ,  H01L24/81 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/351 ,  H05K2201/09909 ,  H05K2201/10454 ,  H05K2201/10484 ,  H05K2201/2036 ,  H05K3/3442 ,  Y02P70/613

Abstract: Bonding pads are formed on a main surface of a semiconductor chip. An insulating layer having openings located on the bonding pads is formed on the main surface of the semiconductor chip. Base metal layers are formed on the bonding pads. A buffer coat film having a portion laid on a periphery of the base metal layer is formed on the insulating layer. Connection layers are formed on the base metal layers. First conductors are formed on the connection layers. A seal resin exposing only top surfaces of the first conductors is formed. Lumpish second conductors are formed on the top surfaces of the first conductor. Thereby, a resin seal semiconductor package can be made compact and it has improved electrical characteristics and high reliability.

Abstract translation: 接合焊盘形成在半导体芯片的主表面上。 在半导体芯片的主表面上形成具有位于接合焊盘上的开口的绝缘层。 在接合焊盘上形成基底金属层。 在绝缘层上形成具有放置在基底金属层周围的部分的缓冲涂膜。 连接层形成在基底金属层上。 第一导体形成在连接层上。 形成仅露出第一导体的顶表面的密封树脂。 在第一导体的顶表面上形成笨重的第二导体。 因此，可以使树脂密封半导体封装紧凑并且具有改善的电特性和高可靠性。

公开(公告)号：US5656863A

公开(公告)日：1997-08-12

申请号：US198078

申请日：1994-02-17

Applicant: Masatoshi Yasunaga ,  Shin Nakao ,  Shinji Baba ,  Mitsuyasu Matsuo ,  Hironori Matsushima

Inventor： Masatoshi Yasunaga ,  Shin Nakao ,  Shinji Baba ,  Mitsuyasu Matsuo ,  Hironori Matsushima

IPC: H01L21/60 ,  H01L21/56 ,  H01L21/68 ,  H01L23/12 ,  H01L23/28 ,  H01L23/31 ,  H01L23/32 ,  H01L23/485 ,  H01L25/10 ,  H05K3/30 ,  H05K3/34 ,  H01L23/48

CPC classification number: H01L21/568 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/3107 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/10 ,  H01L25/105 ,  H05K3/303 ,  H01L2224/0231 ,  H01L2224/0233 ,  H01L2224/02333 ,  H01L2224/02335 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/1131 ,  H01L2224/11332 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/1191 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16105 ,  H01L2224/16108 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/4813 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/812 ,  H01L2224/81801 ,  H01L2224/83104 ,  H01L2225/1005 ,  H01L2225/1035 ,  H01L2225/107 ,  H01L24/45 ,  H01L24/48 ,  H01L24/81 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/351 ,  H05K2201/09909 ,  H05K2201/10454 ,  H05K2201/10484 ,  H05K2201/2036 ,  H05K3/3442 ,  Y02P70/613

Abstract: Bonding pads are formed on a main surface of a semiconductor chip. An insulating layer having openings located on the bonding pads is formed on the main surface of the semiconductor chip. Base metal layers are formed on the bonding pads. A buffer coat film having a portion laid on a periphery of the base metal layer is formed on the insulating layer. Connection layers are formed on the base metal layers. First conductors are formed on the connection layers. A seal resin exposing only top surfaces of the first conductors is formed. Lumpish second conductors are formed on the top surfaces of the first conductor. Thereby, a resin seal semiconductor package can be made compact and it has improved electrical characteristics and high reliability.

Abstract translation: 接合焊盘形成在半导体芯片的主表面上。 在半导体芯片的主表面上形成具有位于接合焊盘上的开口的绝缘层。 在接合焊盘上形成基底金属层。 在绝缘层上形成具有放置在基底金属层周围的部分的缓冲涂膜。 连接层形成在基底金属层上。 第一导体形成在连接层上。 形成仅露出第一导体的顶表面的密封树脂。 在第一导体的顶表面上形成笨重的第二导体。 因此，可以使树脂密封半导体封装紧凑并且具有改善的电特性和高可靠性。

公开(公告)号：US08772952B2

公开(公告)日：2014-07-08

申请号：US12889023

申请日：2010-09-23

Applicant: Masatoshi Yasunaga ,  Hironori Matsushima ,  Kenya Hironaga ,  Soshi Kuroda

Inventor： Masatoshi Yasunaga ,  Hironori Matsushima ,  Kenya Hironaga ,  Soshi Kuroda

IPC: H01L29/40

CPC classification number: H01L24/85 ,  H01L21/561 ,  H01L22/32 ,  H01L23/3128 ,  H01L23/49866 ,  H01L24/03 ,  H01L24/04 ,  H01L24/05 ,  H01L24/27 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05018 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/32145 ,  H01L2224/43 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48482 ,  H01L2224/48499 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48724 ,  H01L2224/48844 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49431 ,  H01L2224/85051 ,  H01L2224/85205 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/10162 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2924/20752 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/48824 ,  H01L2224/48744 ,  H01L2924/20758 ,  H01L2924/2075 ,  H01L2924/00015

Abstract: To improve reliability of a semiconductor device in which wire bonding using a wire made of copper is performed. A semiconductor device is configured so that one of end parts (wide width part) of a copper wire is joined via a bump on a pad (electrode pad) formed over a main surface (first main surface) of a semiconductor chip of the semiconductor device. The bump is made of gold, which is a metal material having a hardness lower than that of copper, and the width of the bump is narrower than the width of the wide width part of the wire.

Abstract translation: 为了提高使用由铜制成的线进行引线接合的半导体器件的可靠性。 半导体器件被配置为使得铜线的端部（宽宽度部分）中的一个通过形成在半导体器件的半导体芯片的主表面（第一主表面）上的焊盘（电极焊盘）上的凸块接合 。 凸起由金制成，其是具有低于铜的硬度的金属材料，并且凸块的宽度比电线的宽幅部分的宽度窄。

公开(公告)号：US08334172B2

公开(公告)日：2012-12-18

申请号：US13023976

申请日：2011-02-09

Applicant: Soshi Kuroda ,  Masatoshi Yasunaga ,  Hironori Matsushima ,  Kenya Hironaga

Inventor： Soshi Kuroda ,  Masatoshi Yasunaga ,  Hironori Matsushima ,  Kenya Hironaga

IPC: H01L21/786 ,  H01L21/60 ,  H01L21/56 ,  H01L21/58 ,  H01L21/00

CPC classification number: H01L24/48 ,  H01L21/4853 ,  H01L23/295 ,  H01L23/296 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/544 ,  H01L24/45 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2223/54406 ,  H01L2223/54486 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32013 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/48644 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2224/838 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85444 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2924/00 ,  H01L2224/78 ,  H01L2924/00012

Abstract: Technology capable of preventing the deterioration of the reliability of semiconductor devices caused by the gasification of a part of the material constituting a wiring substrate is provided. A wiring layer constituting a circuit pattern is formed over each of the front and rear surfaces of a glass epoxy substrate, and after the formation of a solder resist covering the wiring layer while exposing a part of the wiring layer and prior to a heat treatment (first heat treatment) at 100° C. to 150° C. for dehumidification, a heat treatment (second heat treatment) at 160° C. to 230° C. for gasifying and discharging an organic solvent contained in the material constituting a wiring substrate is performed for the wiring substrate.

Abstract translation: 提供了能够防止由构成布线基板的材料的一部分的气化引起的半导体器件的可靠性劣化的技术。 构成电路图案的布线层形成在玻璃环氧树脂基板的前表面和后表面之上，并且在暴露一部分布线层并且在热处理之前形成覆盖布线层的阻焊剂之后 第一热处理）在100℃至150℃下进行除湿，在160℃至230℃下进行热处理（第二热处理），用于气化和排出构成布线基板的材料中所含的有机溶剂 对布线基板进行。