公开(公告)号：US20170243799A1

公开(公告)日：2017-08-24

申请号：US15514753

申请日：2015-09-18

申请人： CORNING PRECISION MATERIALS CO., LTD.

发明人： Joon Soo KIM ,  Hyung Soo MOON ,  Jae Young CHOI

IPC分类号： H01L23/15 ,  H01L23/00

CPC分类号： H01L23/15 ,  H01L23/3735 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/3511 ,  H01L2924/00

摘要： The present invention relates to a substrate for an integrated circuit package and, more specifically, to a substrate for an integrated circuit package, which reduces mismatch of coefficients of thermal expansion with a semiconductor chip, thereby preventing or minimizing warpage during a reflow process. To this end, the present invention provides a substrate for an integrated circuit package which is interposed between a semiconductor chip and a printed circuit board to electrically connect the semiconductor chip to the printed circuit board, the substrate comprising: an ultra-thin glass; a first CTE control layer which is formed on the upper surface of the ultra-thin glass and formed of a material having a coefficient of thermal expansion different from the coefficients of thermal expansion of the semiconductor chip and the ultra-thin glass; a first metal thin plate which is formed on the upper surface of the first CTE control layer and connected to the semiconductor chip; and a second metal thin plate which is formed on the lower surface of the ultra-thin glass and connected to the printed circuit board.

公开(公告)号：US20170213801A1

公开(公告)日：2017-07-27

申请号：US15003812

申请日：2016-01-22

申请人： Micron Technology, Inc.

发明人： Tieh-Chiang Wu ,  Shing-Yih Shih

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L21/78

CPC分类号： H01L24/02 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/147 ,  H01L23/15 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3171 ,  H01L23/49811 ,  H01L23/49827 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/02333 ,  H01L2224/0235 ,  H01L2224/02373 ,  H01L2224/024 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/48225 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2224/81

摘要： A method for fabricating a package-on-package assembly is provided. A carrier with a passivation layer on the carrier is provided. A redistribution layer (RDL) is formed on the passivation layer. The RDL comprises at least one dielectric layer and at least one metal layer. The at least one metal layer comprises a plurality of first bump pads and second bump pads exposed from a top surface of the at least one dielectric layer. The first bump pads are disposed within a chip mounting area, while the second pads are disposed within a peripheral area. At least one chip is then mounted on the first bump pads. The at least one chip is electrically connected to the RDL through first bumps on the first bump pads. A die package is then mounted on the second bump pads. The die package is electrically connected to the RDL through second bumps on the second bump pads.

公开(公告)号：US20170207188A1

公开(公告)日：2017-07-20

申请号：US15476999

申请日：2017-04-01

申请人： Ping-Jung Yang

发明人： Ping-Jung Yang

IPC分类号： H01L23/00 ,  H05B33/08 ,  H01G4/12

CPC分类号： H01L24/30 ,  H01G4/129 ,  H01L23/15 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/13 ,  H01L24/16 ,  H01L24/46 ,  H01L24/48 ,  H01L24/49 ,  H01L25/16 ,  H01L51/0096 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05599 ,  H01L2224/056 ,  H01L2224/05688 ,  H01L2224/05788 ,  H01L2224/13076 ,  H01L2224/1308 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32151 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48228 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H05B33/0896 ,  H05K1/09 ,  Y02E10/549 ,  H01L2924/00014 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/01029

摘要： A substrate comprising a solid glass core having a first surface and a second surface opposed to the first surface; multiple conductors extending through the solid glass core beginning at the first surface and ending at the second surface, wherein one of the conductors has a third surface and a fourth surface, wherein the third surface and the first surface are substantially coplanar, wherein the second surface and the fourth surface are substantially coplanar, wherein one of the conductors comprise a copper-tungsten alloy material, wherein the solid glass core is directly contact with the conductor; and a first dielectric layer and a first metal layer formed at the first surface, wherein the first metal layer at the first surface is electrically coupled with one of the conductors.

公开(公告)号：US20170186710A1

公开(公告)日：2017-06-29

申请号：US15312704

申请日：2015-05-27

申请人： University of Florida Research Foundation, Inc.

发明人： YONG-KYU YOON ,  CHEOLBOK KIM ,  HYUP JONG KIM ,  DAVID ELIECER SENIOR

IPC分类号： H01L23/66 ,  H01P1/203 ,  H01Q1/38 ,  H01P11/00 ,  H01P7/08 ,  H01L23/498 ,  H01L21/48

CPC分类号： H01L23/66 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/49894 ,  H01L2223/6616 ,  H01L2223/6677 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2924/0002 ,  H01P1/20381 ,  H01P7/08 ,  H01P11/003 ,  H01Q1/38 ,  H05K1/0306 ,  H05K2201/10378 ,  H01L2924/00

摘要： Various integrated high quality electronic components and systems, and methods of their manufacture, are presented. In one example, a device includes a glass substrate or interposer including one or more metalized through-glass vias (TGVs). The one or more metalized TGVs can be used to form a substrate integrated waveguide, a complementary split ring resonator, a disc loaded monopole antenna or other device. An array of metalized TGVs can define side walls of the integrated waveguide. A disc coupled to a tip of a metalized TGV can provide capacitive disc loading of the monopole antenna.

公开(公告)号：US20170178946A1

公开(公告)日：2017-06-22

申请号：US15124036

申请日：2015-04-05

申请人： ORBOTECH LTD.

发明人： Michael Zenou ,  Zvi Kotler ,  Jonathan Ankri ,  Abraham Rotnemer ,  Oleg Ermak

IPC分类号： H01L21/70 ,  H05K3/12

CPC分类号： H01L21/705 ,  H01L21/4867 ,  H01L23/15 ,  H05K1/097 ,  H05K3/02 ,  H05K3/105 ,  H05K2203/107 ,  H05K2203/1492

摘要： A method for manufacturing includes coating a substrate (22) with a matrix (28) containing a material to be patterned on the substrate. A pattern is fixed in the matrix by directing a pulsed energy beam to impinge on a locus of the pattern so as to cause adhesion of the material to the substrate along the pattern without fully sintering the material in the pattern. The matrix remaining on the substrate outside the fixed pattern is removed, and after removing the matrix, the material in the pattern is sintered.

公开(公告)号：US20170154860A1

公开(公告)日：2017-06-01

申请号：US15316217

申请日：2015-06-16

申请人： SONY CORPORATION

发明人： KOSUKE HAREYAMA

IPC分类号： H01L23/66 ,  H01P11/00 ,  H01P3/08 ,  H01L21/48 ,  H01L23/498 ,  H01L25/18

CPC分类号： H01L23/66 ,  H01L21/486 ,  H01L23/12 ,  H01L23/15 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49894 ,  H01L25/18 ,  H01L2223/6611 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01P3/081 ,  H01P11/003 ,  H01L2924/00

摘要： The present technology relates to a semiconductor device and a method of manufacturing the semiconductor device capable of realizing impedance control of the semiconductor device.An input/output wiring line 23 and a ground wiring line 22 are such that through glass vias are provided so as to form a strip line structure by blasting or electric discharge machining and thereafter metal films are formed on a surface and a rear surface. It is possible to configure the semiconductor device with the impedance control by adjusting a conductor diameter of the input/output wiring line 23 and an insulating layer thickness between the input/output wiring line 23 and the ground wiring line 22. The present technology may be applied to the semiconductor device.

公开(公告)号：US09634214B2

公开(公告)日：2017-04-25

申请号：US14072387

申请日：2013-11-05

申请人： LedEngin, Inc.

发明人： Xiantao Yan

IPC分类号： H05K1/14 ,  H05K1/00 ,  H01L33/00 ,  H01L31/0203 ,  H01L23/12 ,  H01L23/053 ,  H01L23/14 ,  H01L23/06 ,  H01L23/15 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L33/64 ,  H01L23/495 ,  H01L23/373 ,  H01L21/48 ,  H01L33/48 ,  H01L29/16

CPC分类号： H01L33/641 ,  H01L21/4807 ,  H01L23/15 ,  H01L23/3731 ,  H01L23/49506 ,  H01L29/1606 ,  H01L33/48 ,  H01L33/64 ,  H01L2224/05187 ,  H01L2224/05193 ,  H01L2224/29187 ,  H01L2224/29193 ,  H01L2924/0002 ,  H01L2924/05032 ,  H01L2924/15787 ,  H01L2924/15793 ,  H01L2924/00

摘要： Substrates and packages for LED based light devices can incorporate a material with high thermal conductivity in at least the lateral direction (e.g., graphite or graphene) to spread heat across the surface of the substrate. A substrate or layer in a multi-layer substrate can have a graphite core disposed between ceramic sublayers that provide electrical insulation and thermal conductivity in the transverse direction. Another substrate or layer in a multi-layer substrate can be fabricated using a composite of graphite and ceramic materials.

公开(公告)号：US09615453B2

公开(公告)日：2017-04-04

申请号：US14036256

申请日：2013-09-25

申请人： Ping-Jung Yang

发明人： Ping-Jung Yang

IPC分类号： H05K1/09 ,  H01L23/15 ,  H01L23/49 ,  H01L51/00 ,  H01L23/498 ,  H01L23/00 ,  H01L25/16

CPC分类号： H01L24/30 ,  H01G4/129 ,  H01L23/15 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/13 ,  H01L24/16 ,  H01L24/46 ,  H01L24/48 ,  H01L24/49 ,  H01L25/16 ,  H01L51/0096 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05599 ,  H01L2224/056 ,  H01L2224/05688 ,  H01L2224/05788 ,  H01L2224/13076 ,  H01L2224/1308 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32151 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48228 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H05B33/0896 ,  H05K1/09 ,  Y02E10/549 ,  H01L2924/00014 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/01029

摘要： A substrate comprising a solid glass core having a first surface and a second surface opposed to the first surface; multiple conductors extending through the solid glass core beginning at the first surface and ending at the second surface, wherein one of the conductors has a third surface and a fourth surface, wherein the third surface and the first surface are substantially coplanar, wherein the second surface and the fourth surface are substantially coplanar, wherein one of the conductors comprise a copper-tungsten alloy material, wherein the solid glass core is directly contact with the conductor; and a first dielectric layer and a first metal layer formed at the first surface, wherein the first metal layer at the first surface is electrically coupled with one of the conductors.

公开(公告)号：US20170069596A1

公开(公告)日：2017-03-09

申请号：US15121759

申请日：2014-03-27

申请人： Ravi PILLARISETTY ,  Sansaptak DASGUPTA ,  Niloy MUKHERJEE ,  Brian S. DOYLE ,  Marko RADOSAVLJEVIC ,  Han Wui THEN

发明人： Ravi PILLARISETTY ,  Sansaptak DASGUPTA ,  Niloy MUKHERJEE ,  Brian S. DOYLE ,  Marko RADOSAVLJEVIC ,  Han Wui THEN

IPC分类号： H01L25/065 ,  H01L29/24 ,  H01L29/20 ,  H01L23/498 ,  H01L25/00

CPC分类号： H01L25/0652 ,  G06F1/1652 ,  G09F9/301 ,  G09G3/3648 ,  H01L21/8221 ,  H01L21/8258 ,  H01L23/145 ,  H01L23/15 ,  H01L23/49811 ,  H01L23/4985 ,  H01L25/00 ,  H01L25/50 ,  H01L27/0688 ,  H01L29/2003 ,  H01L29/24 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2924/0002

摘要： Embodiments of the present disclosure describe multi-device flexible systems on a chip (SOCs) and methods for making such SOCs. A multi-material stack may be processed sequentially to form multiple integrated circuit (IC) devices in a single flexible SOC. By forming the IC devices from a single stack, it is possible to form contacts for multiple devices through a single metallization process and for those contacts to be located in a common back-plane of the SOC. Stack layers may be ordered and processed according to processing temperature, such that higher temperature processes are performed earlier. In this manner, intervening layers of the stack may shield some stack layers from elevated processing temperatures associated with processing upper layers of the stack. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例描述了芯片上的多设备灵活系统（SOC）以及用于制造这种SOC的方法。 可以依次处理多材料堆叠，以在单个柔性SOC中形成多个集成电路（IC）装置。 通过从单个堆叠形成IC器件，可以通过单个金属化工艺为多个器件形成触点，并且可以将这些触点位于SOC的公共背面中。 堆叠层可以根据处理温度进行排序和处理，使得较早进行较高温度处理。 以这种方式，堆叠的中间层可以屏蔽一些堆叠层与处理堆叠的上层相关联的升高的处理温度。 可以描述和/或要求保护其他实施例。

公开(公告)号：US09589865B2

公开(公告)日：2017-03-07

申请号：US14811736

申请日：2015-07-28

申请人： Avago Technologies General IP (Singapore) Pte. Ltd.

发明人： Thomas Dungan

IPC分类号： H01L23/42 ,  H01L27/095 ,  H01L27/082 ,  H01L25/065

CPC分类号： H01L23/42 ,  H01L23/15 ,  H01L23/3677 ,  H01L23/49822 ,  H01L24/00 ,  H01L25/0657 ,  H01L27/082 ,  H01L27/085 ,  H01L27/095 ,  H01L2225/06548

摘要： An apparatus, a semiconductor package including the apparatus and a method are disclosed. The apparatus includes a semiconductor die having second stages of power amplifier disposed over a module substrate. The module substrate includes a plurality of layers, pluralities of vias, and pluralities of routing layers for heat dissipation and electrical connections.

摘要翻译： 公开了一种装置，包括该装置的半导体封装和方法。 该装置包括具有设置在模块基板上的功率放大器的第二级的半导体管芯。 模块基板包括多个层，多个通孔，以及用于散热和电连接的多个布线层。