公开(公告)号：US20240113026A1

公开(公告)日：2024-04-04

申请号：US18526127

申请日：2023-12-01

Applicant: Infineon Technologies AG

Inventor： Edward Fürgut ,  Ravi Keshav Joshi ,  Thomas Basler ,  Martin Gruber ,  Jochen Hilsenbeck ,  Wolfgang Scholz

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/00 ,  H01L29/16 ,  H01L29/45

CPC classification number: H01L23/53238 ,  H01L21/7685 ,  H01L24/45 ,  H01L29/1608 ,  H01L29/45 ,  H01L2224/05172 ,  H01L2224/05179 ,  H01L2224/05181 ,  H01L2224/05672 ,  H01L2224/05679 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147

Abstract: A silicon carbide device includes a silicon carbide substrate, a contact layer located on the silicon carbide substrate and including nickel and silicon, a barrier layer structure including titanium and tungsten, and a metallization layer comprising copper, wherein the contact layer is located between the silicon carbide substrate and at least a part of the barrier layer structure, wherein the barrier layer structure is located between the silicon carbide substrate and the metallization layer, wherein the metallization layer is configured as a contact pad of the silicon carbide device.

公开(公告)号：US20180301338A1

公开(公告)日：2018-10-18

申请号：US15950679

申请日：2018-04-11

Applicant: Infineon Technologies AG

Inventor： Jochen Hilsenbeck

IPC: H01L21/04 ,  H01L29/47 ,  H01L29/40 ,  H01L29/45 ,  H01L29/417 ,  H01L23/373

Abstract: A semiconductor device includes a semiconductor substrate with a first side and a second side, and at least one doping region formed at the first side of the semiconductor substrate. The semiconductor device further includes a first metallization structure at the first side of the semiconductor substrate and on and in contact with the at least one doping region, and a second metallization structure at the second side of the semiconductor substrate. The second metallization structure forms a silicide interface region with the semiconductor substrate and a non-silicide interface region with the semiconductor substrate.

公开(公告)号：US09997459B2

公开(公告)日：2018-06-12

申请号：US15427428

申请日：2017-02-08

Applicant: Infineon Technologies AG

Inventor： Jochen Hilsenbeck ,  Jens Peter Konrath ,  Stefan Krivec

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/285 ,  H01L29/20 ,  H01L29/16

CPC classification number: H01L23/53238 ,  H01L21/2855 ,  H01L21/28568 ,  H01L21/28575 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76852 ,  H01L23/532 ,  H01L23/564 ,  H01L24/03 ,  H01L24/05 ,  H01L24/48 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/8083 ,  H01L2224/0345 ,  H01L2224/0347 ,  H01L2224/03612 ,  H01L2224/03614 ,  H01L2224/0391 ,  H01L2224/03914 ,  H01L2224/04042 ,  H01L2224/05018 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05188 ,  H01L2224/05551 ,  H01L2224/05561 ,  H01L2224/05566 ,  H01L2224/05599 ,  H01L2224/05688 ,  H01L2224/45099 ,  H01L2224/85375 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/12036 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/0496 ,  H01L2924/01042 ,  H01L2924/01029 ,  H01L2924/01014 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device includes a semiconductor body having a front face, a back face and an active zone at the front face. A front surface metallization layer having a front face and a back face is disposed over the semiconductor body so that the back face of the front surface metallization layer faces the front face of the semiconductor body and is electrically connected to the active zone. An upper barrier layer made of amorphous molybdenum nitride is disposed on the front face of the front surface metallization layer.

公开(公告)号：US20180019218A1

公开(公告)日：2018-01-18

申请号：US15716534

申请日：2017-09-27

Applicant: Infineon Technologies AG

Inventor： Jens Peter Konrath ,  Jochen Hilsenbeck

IPC: H01L23/00

CPC classification number: H01L24/03 ,  B81C1/00 ,  H01L24/05 ,  H01L24/06 ,  H01L29/40 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03612 ,  H01L2224/03614 ,  H01L2224/0381 ,  H01L2224/0383 ,  H01L2224/0391 ,  H01L2224/05017 ,  H01L2224/05025 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05582 ,  H01L2224/05601 ,  H01L2224/05613 ,  H01L2224/05624 ,  H01L2224/05638 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05663 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05673 ,  H01L2224/06181 ,  H01L2924/01029 ,  H01L2924/01014 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01076 ,  H01L2924/0108

Abstract: According to various embodiments an electronic component includes: at least one electrically conductive contact region; a contact pad including a self-segregating composition disposed over the at least one electrically conductive contact region; a segregation suppression structure disposed between the contact pad and the at least one electrically conductive contact region, wherein the segregation suppression structure includes more nucleation inducing topography features than the at least one electrically conductive contact region for perturbing a chemical segregation of the self-segregating composition by crystallographic interfaces of the contact pad defined by the nucleation inducing topography features.

公开(公告)号：US20220285283A1

公开(公告)日：2022-09-08

申请号：US17752224

申请日：2022-05-24

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Ravi Keshav Joshi ,  Ralf Siemieniec ,  Thomas Basler ,  Martin Gruber ,  Jochen Hilsenbeck ,  Dethard Peters ,  Roland Rupp ,  Wolfgang Scholz

IPC: H01L23/532 ,  H01L29/16 ,  H01L21/768 ,  H01L23/00 ,  H01L29/45

Abstract: A power semiconductor device includes a semiconductor substrate having a wide bandgap semiconductor material and a first surface, an insulation layer above the first surface of the semiconductor substrate, the insulation layer including at least one opening extending through the insulation layer in a vertical direction, a front metallization above the insulation layer with the insulation layer being interposed between the front metallization and the first surface of the semiconductor substrate, and a metal connection arranged in the opening of the insulation layer and electrically conductively connecting the front metallization with the semiconductor substrate; wherein the front metallization includes at least one layer that is a metal or a metal alloy having a higher melting temperature than an intrinsic temperature of the wide bandgap semiconductor material of the semiconductor substrate.

公开(公告)号：US11211303B2

公开(公告)日：2021-12-28

申请号：US16701790

申请日：2019-12-03

Applicant: Infineon Technologies AG

Inventor： Jens Peter Konrath ,  Jochen Hilsenbeck ,  Dethard Peters ,  Paul Salmen ,  Tobias Schmidutz ,  Vice Sodan ,  Christian Stahlhut ,  Juergen Steinbrenner ,  Bernd Zippelius

IPC: H01L29/417 ,  H01L23/31 ,  H01L29/06 ,  H01L29/78 ,  H01L29/739 ,  H01L29/861 ,  H01L23/29 ,  H01L29/16

Abstract: An embodiment of a semiconductor device includes a semiconductor body having a first main surface. The semiconductor body includes an active device area and an edge termination area at least partly surrounding the active device area. The semiconductor device further includes a contact electrode on the first main surface and electrically connected to the active device area. The semiconductor device further includes a passivation structure on the edge termination area and laterally extending into the active device area. The semiconductor device further includes an encapsulation structure on the passivation structure and covering a first edge of the passivation structure above the contact electrode.

公开(公告)号：US11024502B2

公开(公告)日：2021-06-01

申请号：US16419377

申请日：2019-05-22

Applicant: Infineon Technologies AG

Inventor： Jens Peter Konrath ,  Jochen Hilsenbeck

IPC: H01L21/266 ,  H01L21/033 ,  H01L29/10 ,  H01L29/16 ,  H01L29/861 ,  H01L29/78

Abstract: A method for forming a semiconductor device includes forming a mask layer with a first implantation window on a semiconductor substrate and implanting dopants with a first implantation energy into the semiconductor substrate through the first implantation window to form a first portion of a doping region of the semiconductor device. The mask layer is adapted to form a second implantation window of the mask layer. Further, dopants are implanted with a second implantation energy into the semiconductor substrate through the second implantation window. The second implantation energy differs from the first implantation energy and a lateral dimension of the first implantation window differs from a lateral dimension of the second implantation window.

公开(公告)号：US09966348B2

公开(公告)日：2018-05-08

申请号：US15716534

申请日：2017-09-27

Applicant: Infineon Technologies AG

Inventor： Jens Peter Konrath ,  Jochen Hilsenbeck

IPC: H01L23/52 ,  H01L23/00

CPC classification number: H01L24/03 ,  B81C1/00 ,  H01L24/05 ,  H01L24/06 ,  H01L29/40 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03612 ,  H01L2224/03614 ,  H01L2224/0381 ,  H01L2224/0383 ,  H01L2224/0391 ,  H01L2224/05017 ,  H01L2224/05025 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05582 ,  H01L2224/05601 ,  H01L2224/05613 ,  H01L2224/05624 ,  H01L2224/05638 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05663 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05673 ,  H01L2224/06181 ,  H01L2924/01029 ,  H01L2924/01014 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01076 ,  H01L2924/0108

Abstract: According to various embodiments an electronic component includes: at least one electrically conductive contact region; a contact pad including a self-segregating composition disposed over the at least one electrically conductive contact region; a segregation suppression structure disposed between the contact pad and the at least one electrically conductive contact region, wherein the segregation suppression structure includes more nucleation inducing topography features than the at least one electrically conductive contact region for perturbing a chemical segregation of the self-segregating composition by crystallographic interfaces of the contact pad defined by the nucleation inducing topography features.

公开(公告)号：US09685347B2

公开(公告)日：2017-06-20

申请号：US14532129

申请日：2014-11-04

Applicant: Infineon Technologies AG

Inventor： Jochen Hilsenbeck ,  Jens Peter Konrath ,  Stefan Krivec

IPC: H01L23/532 ,  H01L21/3213 ,  H01L21/285 ,  H01L21/768 ,  H01L29/808 ,  H01L29/417 ,  H01L29/10 ,  H01L23/00 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L21/32133 ,  H01L21/2855 ,  H01L21/76843 ,  H01L21/76852 ,  H01L23/53238 ,  H01L24/05 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/8083 ,  H01L2224/022 ,  H01L2224/04042 ,  H01L2224/05007 ,  H01L2224/05547 ,  H01L2224/05647 ,  H01L2224/85375 ,  H01L2924/12036 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/0001 ,  H01L2924/00014

Abstract: A semiconductor device comprises a semiconductor body with a front face and a back face, having an active zone located at the front face, a front surface metallization layer having a front face and a back face directed towards the active zone, the front surface metallization layer being provided on the front face of the semiconductor body and being electrically connected to the active zone, and a first barrier layer, comprising amorphous metal nitride, located between the active zone and the metallization layer. Further, a method for producing such a device is provided.

公开(公告)号：US11217500B2

公开(公告)日：2022-01-04

申请号：US16379289

申请日：2019-04-09

Applicant: Infineon Technologies AG

Inventor： Jens Peter Konrath ,  Wolfgang Bergner ,  Romain Esteve ,  Richard Gaisberger ,  Florian Grasse ,  Jochen Hilsenbeck ,  Ravi Keshav Joshi ,  Stefan Kramp ,  Stefan Krivec ,  Grzegorz Lupina ,  Hiroshi Narahashi ,  Andreas Voerckel ,  Stefan Woehlert

IPC: H01L23/31 ,  H01L23/29 ,  H01L21/56 ,  H01L29/16 ,  H01L29/861 ,  H01L29/78 ,  H01L21/768 ,  H01L23/532

Abstract: A semiconductor device includes a contact metallization layer arranged on a semiconductor substrate, an inorganic passivation structure arranged on the semiconductor substrate, and an organic passivation layer. The organic passivation layer is located between the contact metallization layer and the inorganic passivation structure, and located vertically closer to the semiconductor substrate than a part of the organic passivation layer located on top of the inorganic passivation structure.