公开(公告)号：US20230179418A1

公开(公告)日：2023-06-08

申请号：US17898045

申请日：2022-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungwoo Noh ,  Jisoo Kim ,  Kyungjin Lee ,  Younghyun Ji

IPC: H04L9/32 ,  H04L9/06 ,  H04L9/08

CPC classification number: H04L9/3213 ,  H04L9/0643 ,  H04L9/0861 ,  H04L9/3247

Abstract: A storage device includes a memory device storing data, and a controller controlling the memory device. The controller obtains and stores a certificate including a public key of an administrator from a host device, provides a nonce to the host device in response to a request from the host device, receives a token request signature including the nonce, a user identifier (ID), an allowed command list and a lifetime from the host device, and when it is verified that the token request signature is generated by a legitimate administrator by decrypting the token request signature with the public key, generates a token for allowing a user corresponding to the user ID to execute a command included in the allowed command list during the lifetime, and a token secret key corresponding to the token, and provides the token and the token secret key to the host device.

公开(公告)号：US20230200053A1

公开(公告)日：2023-06-22

申请号：US17945235

申请日：2022-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yangdoo Kim ,  Yonghwan Kim ,  Sangwuk Park ,  Sunghyun Park ,  Jinyoung Park ,  Minkyu Suh ,  Jungpyo Hong

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/34 ,  H10B12/033

Abstract: A semiconductor memory device includes a substrate including a memory cell region, a plurality of capacitor structures arranged in the memory cell region of the substrate and including a plurality of lower electrodes, a capacitor dielectric layer, and an upper electrode, a first support pattern contacting sidewalls of the plurality of lower electrodes of the plurality of capacitor structures to support the plurality of lower electrodes, and a second support pattern located at a higher vertical level than a vertical level of the first support pattern and contacting the sidewalls of the plurality of lower electrodes to support the plurality of lower electrodes. The plurality of lower electrodes have a plurality of recessed electrode portions, respectively, in upper portions of the plurality of lower electrodes.

公开(公告)号：US20230170912A1

公开(公告)日：2023-06-01

申请号：US17964377

申请日：2022-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Baekmin LIM ,  Seungjin KIM ,  Seunghyun OH

IPC: H03L7/197 ,  H03L7/081 ,  H03L7/093

CPC classification number: H03L7/1976 ,  H03L7/081 ,  H03L7/093

Abstract: A fractional divider processing circuitry is to receive one of a plurality of clock signals as an input clock signal, and generate a first division clock signal based on the input clock signal and a first control signal. Phases of the plurality of clock signals partially overlap each other. The processing circuitry generates a delta-sigma modulation signal based on the first division clock signal and a frequency control word, and generates a second division clock signal based on the plurality of clock signals, the first division clock signal and a second control signal. The second control signal corresponds to a quantization noise of the delta-sigma modulation signal. The processing circuitry generates the second control signal and a digital control word based on the quantization noise of the delta-sigma modulator. The processing circuitry generates a final division clock signal based on the second division clock signal and the digital control word.

公开(公告)号：US20250169376A1

公开(公告)日：2025-05-22

申请号：US18664982

申请日：2024-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehyeong LEE ,  Hyeokshin KWON ,  Daeyun KIM ,  Daeseok HAN

IPC: H10N60/01 ,  H10N60/12 ,  H10N60/85

Abstract: A Josephson junction device has a second region between first and third regions, and the Josephson junction device includes: a substrate in the first, second, and third regions; a first superconductive layer arranged on the substrate in the first and second regions and not the third region; a second superconductive layer arranged in the second and third regions and spatially overlapping the first superconductive layer in the second region; an oxide layer sandwiched between the first superconductive layer the second superconductive in the second region; and a first trench in the substrate in the third region, the trench passing under the second superconductive layer in the third region.

公开(公告)号：US20250169187A1

公开(公告)日：2025-05-22

申请号：US18753484

申请日：2024-06-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongsoon PARK ,  Gunpil HWANG ,  Hyonwook RA ,  Keunhee BAI ,  Jinwook LEE ,  Sangho CHEON

IPC: H01L27/02 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: A semiconductor device may include a device isolation layer on a substrate and defining active regions extending a first direction; gate structures intersecting the active regions and extending in a second direction; channel layers spaced apart from each other on the active regions and surrounded by the gate structures; and source/drain regions connected to the channel layers and in recessed regions of the active regions on both sides of the gate structures. First and second regions of the substrate respectively may be spaced apart by a first length and the second length from first ends of the gate structures in the second direction. The second length may be longer than the first length. An upper surface of the device isolation layer may have recessed portion on the first region of the substrate and a flat upper surface on the second region of the substrate.

公开(公告)号：US20250169133A1

公开(公告)日：2025-05-22

申请号：US18635282

申请日：2024-04-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： GYEOM KIM ,  YOON TAE NAM ,  SANG MOON LEE ,  KYUNG BIN CHUN ,  RYONG HA ,  YANG XU

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A semiconductor device is provided. The semiconductor device comprises an active pattern extending in a first direction, a plurality of gate structures on the active pattern and spaced apart in the first direction and a source/drain pattern between adjacent ones of the gate structures, wherein the source/drain pattern includes a semiconductor liner film in contact with the active pattern, a lower semiconductor filling film on the semiconductor liner film, an upper semiconductor filling film on the lower semiconductor filling film, and a semiconductor buffer film between the lower semiconductor filling film and the upper semiconductor filling film, each of the semiconductor liner film, the lower semiconductor filling film, the upper semiconductor filling film, and the semiconductor buffer film includes silicon-germanium, a germanium fraction of the semiconductor buffer film is smaller than a germanium fraction of the upper semiconductor filling film and a germanium fraction of the lower semiconductor filling film.

公开(公告)号：US20250169083A1

公开(公告)日：2025-05-22

申请号：US18944349

申请日：2024-11-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： IN JUNG ,  JONGHYUK KIM ,  BOK-YEON WON

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: A semiconductor device including: a substrate having a portion in a cell array region and a portion in a peripheral circuit region; a peripheral circuit structure including a peripheral circuit, and peripheral circuit wiring connected to the peripheral circuit; and a cell array structure, wherein the cell array structure in the cell array region includes a plurality of bit lines extending in a first direction, a plurality of word lines extending on the plurality of bit lines in a second direction, an active pattern disposed between a first word line and a second word line, a cell landing pad connected to the active pattern, and a cell capacitor, and the cell array structure in the peripheral circuit region includes a conductive pad disposed at the same level as an end of the cell capacitor, and a lower conductive contact plug connecting the conductive pad and the peripheral circuit structure.

公开(公告)号：US20250169062A1

公开(公告)日：2025-05-22

申请号：US18936133

申请日：2024-11-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungmin PARK ,  Jisung KIM ,  Beomjong KIM ,  Hyungsuk JUNG

IPC: H10B12/00 ,  H01L29/51

Abstract: Provided is a semiconductor device including a lower electrode, an upper electrode on the lower electrode, and a dielectric layer structure between the lower electrode and the upper electrode. The dielectric layer structure includes a first dielectric layer in contact with the lower electrode, a second dielectric layer in contact with the first dielectric layer, and a third dielectric layer in contact with the upper electrode. The first dielectric layer, the second dielectric layer, and the third dielectric layer include an anti-ferroelectric material. The anti-ferroelectric material of the first, second, and third dielectric layers are of the same material type, and a silicon dopant is included in a region adjacent to an interface between the first dielectric layer and the lower electrode, and a region adjacent to an interface between the third dielectric layer and the upper electrode.

公开(公告)号：US20250169061A1

公开(公告)日：2025-05-22

申请号：US18933076

申请日：2024-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungjoon Park ,  Terai Masayuki

IPC: H10B12/00

Abstract: A semiconductor device includes a substrate, a bit line extending on the substrate in a first horizontal direction, a first mold layer on the bit line, wherein the first mold layer includes a mold opening portion exposing a portion of an upper surface of the bit line and extends in a second horizontal direction, a channel layer arranged on the bit line, a word line arranged within the mold opening portion and extending in the second horizontal direction, a gate insulating layer arranged between the word line and the channel layer, a capacitor structure on the first mold layer, a contact layer between the channel layer and the capacitor structure, and an auxiliary insulating pattern arranged to overlap the contact layer and the gate insulating layer in the first horizontal direction and extending on the word line in the second horizontal direction.

公开(公告)号：US20250168556A1

公开(公告)日：2025-05-22

申请号：US19027708

申请日：2025-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： G Abhishek KUMAR ,  Abhishek SHARMA ,  Sfurti RAJPUT ,  Shailja SHARMA ,  Anil Kumar SAINI

IPC: H04R1/34 ,  G06V40/16 ,  H04R1/28

Abstract: A system and method for enabling audio steering at an electronic device is provided. The method comprises generating, ultrasonic waves for registering a facial map of a user, and capturing, facial images of the user. Further the method identifies facial features of the user from the captured facial images. The method thereafter registers, ultrasonic signatures, based on the facial features and the facial map of the user. The method includes detecting, a spatial location of two or more ultrasonic signatures associated with two or more facial features of the user within a specified vicinity of an electronic device of the user, to detect user's ears position. The method comprises converging, a first non-audible frequency and second non-audible frequency near the user's ears position for producing an audible range of frequency for the user, wherein the production of the audible range of the frequency enables the audio steering.