公开(公告)号：US20250169083A1

公开(公告)日：2025-05-22

申请号：US18944349

申请日：2024-11-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： IN JUNG ,  JONGHYUK KIM ,  BOK-YEON WON

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: A semiconductor device including: a substrate having a portion in a cell array region and a portion in a peripheral circuit region; a peripheral circuit structure including a peripheral circuit, and peripheral circuit wiring connected to the peripheral circuit; and a cell array structure, wherein the cell array structure in the cell array region includes a plurality of bit lines extending in a first direction, a plurality of word lines extending on the plurality of bit lines in a second direction, an active pattern disposed between a first word line and a second word line, a cell landing pad connected to the active pattern, and a cell capacitor, and the cell array structure in the peripheral circuit region includes a conductive pad disposed at the same level as an end of the cell capacitor, and a lower conductive contact plug connecting the conductive pad and the peripheral circuit structure.

公开(公告)号：US20240233811A9

公开(公告)日：2024-07-11

申请号：US18340216

申请日：2023-06-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DONGGEON KIM ,  BOK-YEON WON ,  SELYUNG YOON ,  JONGHYUK KIM

IPC: G11C11/4091 ,  G11C11/4094 ,  G11C11/4096

CPC classification number: G11C11/4091 ,  G11C11/4094 ,  G11C11/4096

Abstract: A bit line sense amplifier of a semiconductor memory device includes: sense amplifier blocks including a PMOS driver or an NMOS driver that detects and amplifies a signal difference between a bit line and a complimentary bit line, and sequentially arranged in a bit line extending direction; column selection units that connect the bit line and a local input/output line according to a first column selection signal; complimentary column selection units that connect the complimentary bit line and a complimentary local input/output line according to a second column selection signal; column selection lines that transmit the first column selection signal to each of the column selection units; and complimentary column selection lines that transmit the second column selection signal to each of the complimentary column selection units. The column selection units and the complimentary column selection units may be disposed to be distributed between the sense amplifier blocks.

公开(公告)号：US20240135987A1

公开(公告)日：2024-04-25

申请号：US18340216

申请日：2023-06-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DONGGEON KIM ,  BOK-YEON WON ,  SELYUNG YOON ,  JONGHYUK KIM

IPC: G11C11/4091 ,  G11C11/4094 ,  G11C11/4096

CPC classification number: G11C11/4091 ,  G11C11/4094 ,  G11C11/4096

Abstract: A bit line sense amplifier of a semiconductor memory device includes: sense amplifier blocks including a PMOS driver or an NMOS driver that detects and amplifies a signal difference between a bit line and a complimentary bit line, and sequentially arranged in a bit line extending direction; column selection units that connect the bit line and a local input/output line according to a first column selection signal; complimentary column selection units that connect the complimentary bit line and a complimentary local input/output line according to a second column selection signal; column selection lines that transmit the first column selection signal to each of the column selection units; and complimentary column selection lines that transmit the second column selection signal to each of the complimentary column selection units. The column selection units and the complimentary column selection units may be disposed to be distributed between the sense amplifier blocks.