公开(公告)号：US20200372948A1

公开(公告)日：2020-11-26

申请号：US16989207

申请日：2020-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNG-WOOK KIM ,  HYUK-JOON KWON ,  SANG-KEUN HAN ,  BOK-YEON WON

IPC: G11C11/4091 ,  G11C5/02 ,  G11C7/02 ,  G11C11/4094 ,  G11C11/4097

Abstract: A sense amplifier includes a sense amplifying unit, first and second isolation units, and first and second offset cancellation unit. The sense amplifying unit includes a first P-type metal-oxide-semiconductor (PMOS) transistor, a second PMOS transistor, a first N-type metal-oxide-semiconductor (NMOS) transistor, and a second NMOS transistor. In a layout of the sense amplifier, the first and second PMOS transistors are disposed in a central region of the sense amplifier, the first and second NMOS transistors are disposed at opposite sides of the sense amplifier from each other, the first isolation unit and the first offset cancellation unit are disposed between the first PMOS transistor and the first NMOS transistor, and the second isolation unit and the second offset cancellation unit are disposed between the second PMOS transistor and the second NMOS transistor. In other layouts, the locations of the PMOS transistors and NMOS transistors may be reversed.

公开(公告)号：US20250169083A1

公开(公告)日：2025-05-22

申请号：US18944349

申请日：2024-11-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： IN JUNG ,  JONGHYUK KIM ,  BOK-YEON WON

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: A semiconductor device including: a substrate having a portion in a cell array region and a portion in a peripheral circuit region; a peripheral circuit structure including a peripheral circuit, and peripheral circuit wiring connected to the peripheral circuit; and a cell array structure, wherein the cell array structure in the cell array region includes a plurality of bit lines extending in a first direction, a plurality of word lines extending on the plurality of bit lines in a second direction, an active pattern disposed between a first word line and a second word line, a cell landing pad connected to the active pattern, and a cell capacitor, and the cell array structure in the peripheral circuit region includes a conductive pad disposed at the same level as an end of the cell capacitor, and a lower conductive contact plug connecting the conductive pad and the peripheral circuit structure.

公开(公告)号：US20210272618A1

公开(公告)日：2021-09-02

申请号：US17321769

申请日：2021-05-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNG-WOOK KIM ,  HYUK-JOON KWON ,  SANG-KEUN HAN ,  BOK-YEON WON

IPC: G11C11/4091 ,  G11C5/02 ,  G11C7/02 ,  G11C11/4094 ,  G11C11/4097

Abstract: A sense amplifier includes a sense amplifying unit, first and second isolation units, and first and second offset cancellation unit. The sense amplifying unit includes a first P-type metal-oxide-semiconductor (PMOS) transistor, a second PMOS transistor, a first N-type metal-oxide-semiconductor (NMOS) transistor, and a second NMOS transistor. In a layout of the sense amplifier, the first and second PMOS transistors are disposed in a central region of the sense amplifier, the first and second NMOS transistors are disposed at opposite sides of the sense amplifier from each other, the first isolation unit and the first offset cancellation unit are disposed between the first PMOS transistor and the first NMOS transistor, and the second isolation unit and the second offset cancellation unit are disposed between the second PMOS transistor and the second NMOS transistor. In other layouts, the locations of the PMOS transistors and NMOS transistors may be reversed.

公开(公告)号：US20200227111A1

公开(公告)日：2020-07-16

申请号：US16829044

申请日：2020-03-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNG-WOOK KIM ,  HYUK-JOON KWON ,  SANG-KEUN HAN ,  BOK-YEON WON

IPC: G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C5/02 ,  G11C7/02

Abstract: A sense amplifier includes a sense amplifying unit, first and second isolation units, and first and second offset cancellation unit. The sense amplifying unit includes a first P-type metal-oxide-semiconductor (PMOS) transistor, a second PMOS transistor, a first N-type metal-oxide-semiconductor (NMOS) transistor, and a second NMOS transistor. In a layout of the sense amplifier, the first and second PMOS transistors are disposed in a central region of the sense amplifier, the first and second NMOS transistors are disposed at opposite sides of the sense amplifier from each other, the first isolation unit and the first offset cancellation unit are disposed between the first PMOS transistor and the first NMOS transistor, and the second isolation unit and the second offset cancellation unit are disposed between the second PMOS transistor and the second NMOS transistor. In other layouts, the locations of the PMOS transistors and NMOS transistors may be reversed.

公开(公告)号：US20180182449A1

公开(公告)日：2018-06-28

申请号：US15697164

申请日：2017-09-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNG-WOOK KIM ,  HYUK-JOON KWON ,  SANG-KEUN HAN ,  BOK-YEON WON

IPC: G11C11/4091

CPC classification number: G11C11/4091 ,  G11C5/02 ,  G11C5/025 ,  G11C5/06 ,  G11C7/02 ,  G11C7/06 ,  G11C11/4082 ,  G11C11/4087 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4097 ,  G11C2207/002

Abstract: A sense amplifier includes a sense amplifying unit, first and second isolation units, and first and second offset cancellation unit. The sense amplifying unit includes a first P-type metal-oxide-semiconductor (PMOS) transistor, a second PMOS transistor, a first N-type metal-oxide-semiconductor (NMOS) transistor, and a second NMOS transistor. In a layout of the sense amplifier, the first and second PMOS transistors are disposed in a central region of the sense amplifier, the first and second NMOS transistors are disposed at opposite sides of the sense amplifier from each other, the first isolation unit and the first offset cancellation unit are disposed between the first PMOS transistor and the first NMOS transistor, and the second isolation unit and the second offset cancellation unit are disposed between the second PMOS transistor and the second NMOS transistor. In other layouts, the locations of the PMOS transistors and NMOS transistors may be reversed.

公开(公告)号：US20240135987A1

公开(公告)日：2024-04-25

申请号：US18340216

申请日：2023-06-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DONGGEON KIM ,  BOK-YEON WON ,  SELYUNG YOON ,  JONGHYUK KIM

IPC: G11C11/4091 ,  G11C11/4094 ,  G11C11/4096

CPC classification number: G11C11/4091 ,  G11C11/4094 ,  G11C11/4096

Abstract: A bit line sense amplifier of a semiconductor memory device includes: sense amplifier blocks including a PMOS driver or an NMOS driver that detects and amplifies a signal difference between a bit line and a complimentary bit line, and sequentially arranged in a bit line extending direction; column selection units that connect the bit line and a local input/output line according to a first column selection signal; complimentary column selection units that connect the complimentary bit line and a complimentary local input/output line according to a second column selection signal; column selection lines that transmit the first column selection signal to each of the column selection units; and complimentary column selection lines that transmit the second column selection signal to each of the complimentary column selection units. The column selection units and the complimentary column selection units may be disposed to be distributed between the sense amplifier blocks.

公开(公告)号：US20200118614A1

公开(公告)日：2020-04-16

申请号：US16707738

申请日：2019-12-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNG-WOOK KIM ,  HYUK-JOON KWON ,  SANG-KEUN HAN ,  BOK-YEON WON

IPC: G11C11/4091 ,  G11C11/4097 ,  G11C11/4094 ,  G11C7/02 ,  G11C5/02

Abstract: A sense amplifier includes a sense amplifying unit, first and second isolation units, and first and second offset cancellation unit. The sense amplifying unit includes a first P-type metal-oxide-semiconductor (PMOS) transistor, a second PMOS transistor, a first N-type metal-oxide-semiconductor (NMOS) transistor, and a second NMOS transistor. In a layout of the sense amplifier, the first and second PMOS transistors are disposed in a central region of the sense amplifier, the first and second NMOS transistors are disposed at opposite sides of the sense amplifier from each other, the first isolation unit and the first offset cancellation unit are disposed between the first PMOS transistor and the first NMOS transistor, and the second isolation unit and the second offset cancellation unit are disposed between the second PMOS transistor and the second NMOS transistor. In other layouts, the locations of the PMOS transistors and NMOS transistors may be reversed.

公开(公告)号：US20240233811A9

公开(公告)日：2024-07-11

申请号：US18340216

申请日：2023-06-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DONGGEON KIM ,  BOK-YEON WON ,  SELYUNG YOON ,  JONGHYUK KIM

IPC: G11C11/4091 ,  G11C11/4094 ,  G11C11/4096

CPC classification number: G11C11/4091 ,  G11C11/4094 ,  G11C11/4096

Abstract: A bit line sense amplifier of a semiconductor memory device includes: sense amplifier blocks including a PMOS driver or an NMOS driver that detects and amplifies a signal difference between a bit line and a complimentary bit line, and sequentially arranged in a bit line extending direction; column selection units that connect the bit line and a local input/output line according to a first column selection signal; complimentary column selection units that connect the complimentary bit line and a complimentary local input/output line according to a second column selection signal; column selection lines that transmit the first column selection signal to each of the column selection units; and complimentary column selection lines that transmit the second column selection signal to each of the complimentary column selection units. The column selection units and the complimentary column selection units may be disposed to be distributed between the sense amplifier blocks.

公开(公告)号：US20220328093A1

公开(公告)日：2022-10-13

申请号：US17585865

申请日：2022-01-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SOO BONG CHANG ,  YOUNG-IL LIM ,  BOK-YEON WON ,  SEOK JAE LEE ,  DONG GEON KIM ,  MYEONG SIK RYU ,  IN SEOK BAEK ,  KYOUNG MIN KIM ,  SANG WOOK PARK

IPC: G11C11/4091 ,  G11C11/4094

Abstract: A bitline sense amplifier including: an amplifier which is connected between a first sensing bitline and a second sensing bitline, and detects and amplifies a voltage difference between a first bitline and a second bitline in response to a first control signal and a second control signal; and an equalizer which is connected between a first supply line through which the first control signal is supplied and a second supply line through which the second control signal is supplied, and pre-charges the first bitline and the second bitline with a precharge voltage in response to an equalizing control signal, wherein the equalizer includes an equalizing enable transistor in which a source terminal is connected to the first supply line and performs equalizing in response to the equalizing control signal.

公开(公告)号：US20190189191A1

公开(公告)日：2019-06-20

申请号：US16116079

申请日：2018-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： BOK-YEON WON ,  HYUCK-JOON KWON

IPC: G11C11/4091 ,  G11C7/08 ,  G11C11/408 ,  G11C8/14 ,  G11C7/18

CPC classification number: G11C11/4091 ,  G11C5/025 ,  G11C7/02 ,  G11C7/08 ,  G11C7/18 ,  G11C8/14 ,  G11C11/4087 ,  G11C11/4094 ,  G11C11/4097

Abstract: A layout structure of a bit line sense amplifier in a semiconductor memory device includes a first bit line sense amplifier which is connected to a first bit line and a first complementary bit line, and is controlled via a first control line and a second control line. The first control line is connected to a first node of the first bit line sense amplifier and the second control line is connected to a second node of the first bit line sense amplifier, and the first bit line sense amplifier includes at least one pair of transistors configured to share any one of a first active region corresponding to the first node and a second active region corresponding to the second node.