公开(公告)号：US20210272618A1

公开(公告)日：2021-09-02

申请号：US17321769

申请日：2021-05-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNG-WOOK KIM ,  HYUK-JOON KWON ,  SANG-KEUN HAN ,  BOK-YEON WON

IPC: G11C11/4091 ,  G11C5/02 ,  G11C7/02 ,  G11C11/4094 ,  G11C11/4097

Abstract: A sense amplifier includes a sense amplifying unit, first and second isolation units, and first and second offset cancellation unit. The sense amplifying unit includes a first P-type metal-oxide-semiconductor (PMOS) transistor, a second PMOS transistor, a first N-type metal-oxide-semiconductor (NMOS) transistor, and a second NMOS transistor. In a layout of the sense amplifier, the first and second PMOS transistors are disposed in a central region of the sense amplifier, the first and second NMOS transistors are disposed at opposite sides of the sense amplifier from each other, the first isolation unit and the first offset cancellation unit are disposed between the first PMOS transistor and the first NMOS transistor, and the second isolation unit and the second offset cancellation unit are disposed between the second PMOS transistor and the second NMOS transistor. In other layouts, the locations of the PMOS transistors and NMOS transistors may be reversed.

公开(公告)号：US20200372948A1

公开(公告)日：2020-11-26

申请号：US16989207

申请日：2020-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNG-WOOK KIM ,  HYUK-JOON KWON ,  SANG-KEUN HAN ,  BOK-YEON WON

IPC: G11C11/4091 ,  G11C5/02 ,  G11C7/02 ,  G11C11/4094 ,  G11C11/4097

Abstract: A sense amplifier includes a sense amplifying unit, first and second isolation units, and first and second offset cancellation unit. The sense amplifying unit includes a first P-type metal-oxide-semiconductor (PMOS) transistor, a second PMOS transistor, a first N-type metal-oxide-semiconductor (NMOS) transistor, and a second NMOS transistor. In a layout of the sense amplifier, the first and second PMOS transistors are disposed in a central region of the sense amplifier, the first and second NMOS transistors are disposed at opposite sides of the sense amplifier from each other, the first isolation unit and the first offset cancellation unit are disposed between the first PMOS transistor and the first NMOS transistor, and the second isolation unit and the second offset cancellation unit are disposed between the second PMOS transistor and the second NMOS transistor. In other layouts, the locations of the PMOS transistors and NMOS transistors may be reversed.

公开(公告)号：US20190138233A1

公开(公告)日：2019-05-09

申请号：US16057849

申请日：2018-08-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KUI-YON MUN ,  YOUNG-WOOK KIM ,  WAN-SOO CHOI

IPC: G06F3/06

Abstract: A method of controlling memory devices of a memory controller, the memory devices including a plurality of memory dies, includes receiving at least one data operation request and a power budget from external of the memory controller; determining respective data operation times of the plurality of memory dies, wherein a power consumption due to at least one data operation in response to the at least one data operation request may be equal to or less than the power budget; and controlling the plurality of memory dies based on the data operation times.

公开(公告)号：US20190180811A1

公开(公告)日：2019-06-13

申请号：US16256883

申请日：2019-01-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNG-WOOK KIM ,  HYUK-JOON KWON ,  SANG-KEUN HAN ,  BOK-YEON WON

IPC: G11C11/4091 ,  G11C7/02 ,  G11C11/4094 ,  G11C11/4097 ,  G11C5/02

CPC classification number: G11C11/4091 ,  G11C5/02 ,  G11C5/025 ,  G11C5/06 ,  G11C7/02 ,  G11C7/06 ,  G11C11/4082 ,  G11C11/4087 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4097 ,  G11C2207/002

Abstract: A sense amplifier includes a sense amplifying unit, first and second isolation units, and first and second offset cancellation unit. The sense amplifying unit includes a first P-type metal-oxide-semiconductor (PMOS) transistor, a second PMOS transistor, a first N-type metal-oxide-semiconductor (NMOS) transistor, and a second NMOS transistor. In a layout of the sense amplifier, the first and second PMOS transistors are disposed in a central region of the sense amplifier, the first and second NMOS transistors are disposed at opposite sides of the sense amplifier from each other, the first isolation unit and the first offset cancellation unit are disposed between the first PMOS transistor and the first NMOS transistor, and the second isolation unit and the second offset cancellation unit are disposed between the second PMOS transistor and the second NMOS transistor. In other layouts, the locations of the PMOS transistors and NMOS transistors may be reversed.

公开(公告)号：US20200227111A1

公开(公告)日：2020-07-16

申请号：US16829044

申请日：2020-03-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNG-WOOK KIM ,  HYUK-JOON KWON ,  SANG-KEUN HAN ,  BOK-YEON WON

IPC: G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C5/02 ,  G11C7/02

Abstract: A sense amplifier includes a sense amplifying unit, first and second isolation units, and first and second offset cancellation unit. The sense amplifying unit includes a first P-type metal-oxide-semiconductor (PMOS) transistor, a second PMOS transistor, a first N-type metal-oxide-semiconductor (NMOS) transistor, and a second NMOS transistor. In a layout of the sense amplifier, the first and second PMOS transistors are disposed in a central region of the sense amplifier, the first and second NMOS transistors are disposed at opposite sides of the sense amplifier from each other, the first isolation unit and the first offset cancellation unit are disposed between the first PMOS transistor and the first NMOS transistor, and the second isolation unit and the second offset cancellation unit are disposed between the second PMOS transistor and the second NMOS transistor. In other layouts, the locations of the PMOS transistors and NMOS transistors may be reversed.

公开(公告)号：US20180182449A1

公开(公告)日：2018-06-28

申请号：US15697164

申请日：2017-09-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNG-WOOK KIM ,  HYUK-JOON KWON ,  SANG-KEUN HAN ,  BOK-YEON WON

IPC: G11C11/4091

CPC classification number: G11C11/4091 ,  G11C5/02 ,  G11C5/025 ,  G11C5/06 ,  G11C7/02 ,  G11C7/06 ,  G11C11/4082 ,  G11C11/4087 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4097 ,  G11C2207/002

Abstract: A sense amplifier includes a sense amplifying unit, first and second isolation units, and first and second offset cancellation unit. The sense amplifying unit includes a first P-type metal-oxide-semiconductor (PMOS) transistor, a second PMOS transistor, a first N-type metal-oxide-semiconductor (NMOS) transistor, and a second NMOS transistor. In a layout of the sense amplifier, the first and second PMOS transistors are disposed in a central region of the sense amplifier, the first and second NMOS transistors are disposed at opposite sides of the sense amplifier from each other, the first isolation unit and the first offset cancellation unit are disposed between the first PMOS transistor and the first NMOS transistor, and the second isolation unit and the second offset cancellation unit are disposed between the second PMOS transistor and the second NMOS transistor. In other layouts, the locations of the PMOS transistors and NMOS transistors may be reversed.

公开(公告)号：US20200118614A1

公开(公告)日：2020-04-16

申请号：US16707738

申请日：2019-12-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNG-WOOK KIM ,  HYUK-JOON KWON ,  SANG-KEUN HAN ,  BOK-YEON WON

IPC: G11C11/4091 ,  G11C11/4097 ,  G11C11/4094 ,  G11C7/02 ,  G11C5/02

Abstract: A sense amplifier includes a sense amplifying unit, first and second isolation units, and first and second offset cancellation unit. The sense amplifying unit includes a first P-type metal-oxide-semiconductor (PMOS) transistor, a second PMOS transistor, a first N-type metal-oxide-semiconductor (NMOS) transistor, and a second NMOS transistor. In a layout of the sense amplifier, the first and second PMOS transistors are disposed in a central region of the sense amplifier, the first and second NMOS transistors are disposed at opposite sides of the sense amplifier from each other, the first isolation unit and the first offset cancellation unit are disposed between the first PMOS transistor and the first NMOS transistor, and the second isolation unit and the second offset cancellation unit are disposed between the second PMOS transistor and the second NMOS transistor. In other layouts, the locations of the PMOS transistors and NMOS transistors may be reversed.