公开(公告)号：US20250169133A1

公开(公告)日：2025-05-22

申请号：US18635282

申请日：2024-04-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： GYEOM KIM ,  YOON TAE NAM ,  SANG MOON LEE ,  KYUNG BIN CHUN ,  RYONG HA ,  YANG XU

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A semiconductor device is provided. The semiconductor device comprises an active pattern extending in a first direction, a plurality of gate structures on the active pattern and spaced apart in the first direction and a source/drain pattern between adjacent ones of the gate structures, wherein the source/drain pattern includes a semiconductor liner film in contact with the active pattern, a lower semiconductor filling film on the semiconductor liner film, an upper semiconductor filling film on the lower semiconductor filling film, and a semiconductor buffer film between the lower semiconductor filling film and the upper semiconductor filling film, each of the semiconductor liner film, the lower semiconductor filling film, the upper semiconductor filling film, and the semiconductor buffer film includes silicon-germanium, a germanium fraction of the semiconductor buffer film is smaller than a germanium fraction of the upper semiconductor filling film and a germanium fraction of the lower semiconductor filling film.

公开(公告)号：US20230163213A1

公开(公告)日：2023-05-25

申请号：US17843970

申请日：2022-06-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： SANGGIL LEE ,  SEOKHOON KIM ,  SUNGMIN KIM ,  JUNGTAEK KIM ,  PANKWI PARK ,  DONGSUK SHIN ,  NAMKYU CHO ,  RYONG HA ,  YANG XU

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/49 ,  H01L29/417 ,  H01L21/02

CPC classification number: H01L29/785 ,  H01L29/7848 ,  H01L29/42312 ,  H01L29/49 ,  H01L29/41791 ,  H01L21/02233 ,  H01L21/02532

Abstract: Disclosed is a semiconductor device comprising a substrate including first and second PMOSFET regions, first and second active patterns on the first and second PMOSFET regions, first and second channel patterns on the first and second active patterns and each including semiconductor patterns, and first and second source/drain patterns connected to the first and second channel patterns. The first active pattern includes a first lower semiconductor layer, a first middle semiconductor layer, and a first upper semiconductor layer. Each of the first and second lower semiconductor layers includes silicon. The first middle semiconductor layer includes silicon-germanium. The first middle semiconductor layer has a width that decreases in a downward direction to a maximum value and then increases in the downward direction.

公开(公告)号：US20230111579A1

公开(公告)日：2023-04-13

申请号：US17815187

申请日：2022-07-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： RYONG HA ,  SEOKHOON KIM ,  DOHYUN GO ,  JUNGTAEK KIM ,  MOON SEUNG YANG ,  SANGIL LEE ,  SEOJIN JEONG

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/775 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/417 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/40

Abstract: A semiconductor device includes a substrate that includes an active pattern, a channel pattern disposed on the active pattern, where the channel pattern includes a plurality of semiconductor patterns that are vertically stacked and spaced apart from each other, a source/drain pattern connected to the semiconductor patterns, and a gate electrode disposed on the semiconductor patterns. The gate electrode includes a plurality of portions that are respectively interposed between the semiconductor patterns, and the source/drain pattern includes a buffer layer in contact with the semiconductor patterns and a main layer disposed on the buffer layer. The buffer layer contains silicon germanium (SiGe) and includes a first semiconductor layer and a first reflow layer thereon. A germanium concentration of the first reflow layer is less than that of the first semiconductor layer.

公开(公告)号：US20160380082A1

公开(公告)日：2016-12-29

申请号：US15138234

申请日：2016-04-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYUN-KWAN YU ,  DONG-SUK SHIN ,  WOON-KI SHIN ,  CHEOL-WOO PARK ,  RYONG HA ,  HAN-JIN LIM

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/06 ,  H01L21/3213

CPC classification number: H01L29/66795 ,  H01L21/02068 ,  H01L21/32134 ,  H01L29/66545 ,  H01L29/7848

Abstract: A method of manufacturing a semiconductor device includes forming an active fin extending longitudinally in a first direction along a surface of a substrate, forming a field insulating layer on the substrate, the field insulating layer covering a part of the active fin, forming a dummy gate electrode on the field insulating layer and the active fin, the dummy gate electrode extending in a second direction different from the first direction, forming a spacer on the sides of the dummy gate electrode, and removing the dummy gate electrode by a wet etching process that includes rinsing the dummy gate electrode intermittently during an etching away of the dummy gate electrode.

Abstract translation: 一种制造半导体器件的方法包括：形成沿衬底表面沿第一方向纵向延伸的有效鳍，在衬底上形成场绝缘层，所述场绝缘层覆盖有源散热片的一部分，形成虚拟栅极 所述虚拟栅极电极沿与第一方向不同的第二方向延伸，在所述虚拟栅电极的侧面形成间隔物，并通过湿式蚀刻工艺除去所述伪栅电极， 包括在伪栅极电极的蚀刻离开期间间歇地冲洗虚拟栅电极。