公开(公告)号：US20240387717A1

公开(公告)日：2024-11-21

申请号：US18513853

申请日：2023-11-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYOHOON BYEON ,  SEOKHOON KIM ,  YUYEONG JO ,  PANKWI PARK ,  SUNGKEUN LIM

IPC: H01L29/775 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device includes: a substrate including an active pattern; a first channel structure overlapping the active pattern; a gate electrode including an electrode portion between the active pattern and the first channel structure; a semiconductor layer contacting the first channel structure; and a source/drain pattern contacting the first channel structure, wherein the first channel structure includes: a first upper channel layer; a first lower channel layer; and a first intervening channel layer disposed between the first upper channel layer and the first lower channel layer, wherein the semiconductor layer contacts a sidewall of the first upper channel layer, a sidewall of the first lower channel layer, and a sidewall of the first intervening channel layer, and wherein the semiconductor layer and the first intervening channel layer include a semiconductor material that is different from a semiconductor material of the first upper channel layer and the first lower channel layer.

公开(公告)号：US20230163213A1

公开(公告)日：2023-05-25

申请号：US17843970

申请日：2022-06-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： SANGGIL LEE ,  SEOKHOON KIM ,  SUNGMIN KIM ,  JUNGTAEK KIM ,  PANKWI PARK ,  DONGSUK SHIN ,  NAMKYU CHO ,  RYONG HA ,  YANG XU

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/49 ,  H01L29/417 ,  H01L21/02

CPC classification number: H01L29/785 ,  H01L29/7848 ,  H01L29/42312 ,  H01L29/49 ,  H01L29/41791 ,  H01L21/02233 ,  H01L21/02532

Abstract: Disclosed is a semiconductor device comprising a substrate including first and second PMOSFET regions, first and second active patterns on the first and second PMOSFET regions, first and second channel patterns on the first and second active patterns and each including semiconductor patterns, and first and second source/drain patterns connected to the first and second channel patterns. The first active pattern includes a first lower semiconductor layer, a first middle semiconductor layer, and a first upper semiconductor layer. Each of the first and second lower semiconductor layers includes silicon. The first middle semiconductor layer includes silicon-germanium. The first middle semiconductor layer has a width that decreases in a downward direction to a maximum value and then increases in the downward direction.