公开(公告)号：US11677353B2

公开(公告)日：2023-06-13

申请号：US17539408

申请日：2021-12-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongchang Choi ,  Sungjoon Park ,  Hyoeun Park ,  Youngchang An ,  Hyotae Choo ,  Somin Lee

IPC: H03B5/12

CPC classification number: H03B5/1206 ,  H03B5/1253 ,  H03B2200/004 ,  H03B2200/0086

Abstract: A variable capacitor circuit includes a capacitor block including a first varactor element comprising a first transistor having a first size, a second varactor element comprising a second transistor having a second size different from the first size, a first terminal commonly connected to a source and a drain of the first transistor, a second terminal commonly connected to a source and a drain of the second transistor, and an RC circuit connected to a gate of the first transistor and a gate of the second transistor.

公开(公告)号：US20220311382A1

公开(公告)日：2022-09-29

申请号：US17539408

申请日：2021-12-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongchang Choi ,  Sungjoon Park ,  Hyoeun Park ,  Youngchang An ,  Hyotae Choo ,  Somin Lee

IPC: H03B5/12

Abstract: A variable capacitor circuit includes a capacitor block including a first varactor element comprising a first transistor having a first size, a second varactor element comprising a second transistor having a second size different from the first size, a first terminal commonly connected to a source and a drain of the first transistor, a second terminal commonly connected to a source and a drain of the second transistor, and an RC circuit connected to a gate of the first transistor and a gate of the second transistor.

公开(公告)号：US20250169061A1

公开(公告)日：2025-05-22

申请号：US18933076

申请日：2024-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungjoon Park ,  Terai Masayuki

IPC: H10B12/00

Abstract: A semiconductor device includes a substrate, a bit line extending on the substrate in a first horizontal direction, a first mold layer on the bit line, wherein the first mold layer includes a mold opening portion exposing a portion of an upper surface of the bit line and extends in a second horizontal direction, a channel layer arranged on the bit line, a word line arranged within the mold opening portion and extending in the second horizontal direction, a gate insulating layer arranged between the word line and the channel layer, a capacitor structure on the first mold layer, a contact layer between the channel layer and the capacitor structure, and an auxiliary insulating pattern arranged to overlap the contact layer and the gate insulating layer in the first horizontal direction and extending on the word line in the second horizontal direction.