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    SEMICONDUCTOR DEVICE INCLUDING CAPACITOR
    1.
    发明公开
    SEMICONDUCTOR DEVICE INCLUDING CAPACITOR 审中-公开

    公开(公告)号：US20240237332A1

    公开(公告)日：2024-07-11

    申请号：US18394884

    申请日：2023-12-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jungmin PARK ,  Hanjin LIM ,  Hyungsuk JUNG

    IPC: H10B12/00

    CPC classification number: H10B12/315 ,  H01L28/60 ,  H10B12/34

    Abstract: A semiconductor device includes a structure including a conductive region, and a capacitor electrically connected to the conductive region of the structure. The capacitor includes a first electrode electrically connected to the conductive region, a second electrode on the first electrode, and a dielectric layer between the first electrode and the second electrode. At least one of the first electrode and the second electrode includes a first material layer including a first material region including a first crystalline region and a second crystalline region different from the first crystalline region, and a second material region between the first crystalline region and the second crystalline region, and a second material layer on the first material layer. At least a portion of the first material layer is between the second material layer and the dielectric layer. A material of the first material region is different from a material of the second material region.

    SEMICONDUCTOR DEVICE
    2.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20230337414A1

    公开(公告)日：2023-10-19

    申请号：US18300180

    申请日：2023-04-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jungmin PARK ,  Hanjin LIM ,  Hyungsuk JUNG

    IPC: H10B12/00

    CPC classification number: H10B12/315

    Abstract: A semiconductor device includes a cell capacitor disposed on a substrate and that and includes a first electrode, a dielectric layer structure, and a second electrode. The dielectric layer structure includes a first dielectric layer disposed on the first electrode and that includes a ferroelectric material, a second dielectric layer disposed on the first dielectric layer and that includes an antiferroelectric material, and dielectric particles dispersed in at least one of the first dielectric layer or the second dielectric layer and that include a paraelectric material.

    INTEGRATED CIRCUIT DEVICE
    3.
    发明公开
    INTEGRATED CIRCUIT DEVICE 审中-公开

    公开(公告)号：US20240213302A1

    公开(公告)日：2024-06-27

    申请号：US18394644

    申请日：2023-12-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jungmin PARK ,  Hanjin LIM ,  Hyungsuk JUNG

    IPC: H01G4/08

    CPC classification number: H01L28/40 ,  H10B12/315

    Abstract: An integrated circuit device may include a transistor on a substrate and a capacitor structure electrically connected to the transistor. The capacitor structure may include a first electrode, a dielectric layer structure on the first electrode, and a second electrode on the dielectric layer structure. The dielectric layer structure may include a plurality of first dielectric layers and a plurality of second dielectric layers that are alternately stacked. The plurality of first dielectric layers may include a ferroelectric material, and the plurality of second dielectric layers may include an anti-ferroelectric material. The distribution proportion of internal defect dipoles gradually may vary in a thickness direction of the dielectric layer structure.

    INTEGRATED CIRCUIT DEVICE
    4.
    发明公开
    INTEGRATED CIRCUIT DEVICE 审中-公开

    公开(公告)号：US20230320075A1

    公开(公告)日：2023-10-05

    申请号：US17979187

    申请日：2022-11-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jungmin PARK ,  Hanjin LIM ,  Hyungsuk JUNG

    IPC: H10B12/00

    CPC classification number: H10B12/315 ,  H10B12/033

    Abstract: An integrated circuit (IC) device includes a lower electrode on a substrate. The lower electrode includes a metal-containing film including a first metal. A dielectric film covers the lower electrode. An upper electrode faces the lower electrode with the dielectric film therebetween. The lower electrode includes a main lower electrode layer including no metal dopant of a different type from the first metal. The main lower electrode layer is apart from the dielectric film. An interfacial lower electrode layer is in contact with the dielectric film and includes a first metal dopant and a second metal dopant. The first metal dopant is in a first valence state and includes a second metal, which is different from the first metal. The second metal dopant is in a second valence state, which is less than the first valence state, and includes a third metal, which is different from the first and second metals.

    INTEGRATED CIRCUIT DEVICE
    7.
    发明公开
    INTEGRATED CIRCUIT DEVICE 审中-公开

    公开(公告)号：US20240072106A1

    公开(公告)日：2024-02-29

    申请号：US18238028

    申请日：2023-08-25

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jungmin PARK ,  Hanjin LIM ,  Hyungsuk JUNG

    IPC: H10B53/10 ,  H10B53/30

    CPC classification number: H01L28/56 ,  H10B53/10 ,  H10B53/30

    Abstract: An integrated circuit device may include a transistor on a substrate, and a capacitor structure electrically connected to the transistor. The capacitor structure may include a first electrode, a dielectric layer structure on the first electrode, and a second electrode on the dielectric layer structure. The dielectric layer structure may include a plurality of first dielectric layers and a plurality of second dielectric layers which are alternately stacked. Each of the plurality of first dielectric layers may include an anti-ferroelectric material, and each of the plurality of second dielectric layers includes Hf1-xZrxO2 in which 0

    SEMICONDUCTOR DEVICES
    8.
    发明公开
    SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20230380141A1

    公开(公告)日：2023-11-23

    申请号：US18169721

    申请日：2023-02-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jungmin PARK ,  Hanjin LIM ,  Hyungsuk JUNG

    IPC: H10B12/00

    CPC classification number: H10B12/315 ,  H10B12/033

    Abstract: A semiconductor device includes an upper electrode, a lower electrode, a dielectric layer between the upper electrode and the lower electrode, and a low-bandgap interfacial layer including at least one of a first low-bandgap interfacial layer between the dielectric layer and the upper electrode and a second low-bandgap interfacial layer between the dielectric layer and the lower electrode, wherein each of the first low-bandgap interfacial layer and the second low-bandgap interfacial layer includes a metal oxide having a bandgap energy of more than about 2.5 eV and less than or equal to about 3.5 eV.

    SEMICONDUCTOR MEMORY DEVICE
    9.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20240315045A1

    公开(公告)日：2024-09-19

    申请号：US18495038

    申请日：2023-10-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jungmin PARK ,  Ji-Sung KIM ,  Hanjin LIM ,  Hyungsuk JUNG

    IPC: H10B53/30

    CPC classification number: H10B53/30

    Abstract: A semiconductor device may include a substrate including a first impurity region and a second impurity region; a first word line in a region of the substrate with the first impurity region on one side of the first word line and the second impurity region on an other side of the first word line; a bit line connected to the first impurity region; a first conductive pattern connected to the second impurity region; a first partial electrode and a second partial electrode on the first conductive pattern; a first dielectric layer in contact with an upper surface of the first partial electrode and an upper surface of the second partial electrode; and a common electrode on the first dielectric layer. An area of the upper surface of the first partial electrode may be different from an area of the upper surface of the second partial electrode.

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