公开(公告)号：US12002686B2

公开(公告)日：2024-06-04

申请号：US17004202

申请日：2020-08-27

申请人： KIOXIA CORPORATION

发明人： Satoshi Tsukiyama ,  Satoru Takaku ,  Yuki Sugo ,  Ayana Amano

IPC分类号： H01L25/065 ,  H01L21/50 ,  H01L23/16 ,  H01L21/603 ,  H01L23/29 ,  H01L23/31 ,  H01L25/00

CPC分类号： H01L21/50 ,  H01L23/16 ,  H01L25/0657 ,  H01L21/603 ,  H01L23/295 ,  H01L23/3142 ,  H01L25/50

摘要： A semiconductor device includes a substrate, a first adhesive layer, a first semiconductor chip, and a second adhesive layer. The first adhesive layer is provided above a first surface of the substrate and includes a plurality of types of resins having different molecular weights and a filler. The first semiconductor chip is provided above the first adhesive layer. The second adhesive layer is provided in at least a part of a first region between the substrate and the first adhesive layer, and the second adhesive layer includes at least one type of resins among the plurality of types of resins having a molecular weight smaller than a molecular weight of other types of resins among the plurality of types of resins, and a filler having a lower concentration than that of the first adhesive layer.

公开(公告)号：US20230411322A1

公开(公告)日：2023-12-21

申请号：US18176189

申请日：2023-02-28

申请人： Kioxia Corporation

发明人： Hiroaki ASHIDATE ,  Tomoyuki TAKEISHI

IPC分类号： H01L23/00 ,  H01L21/768 ,  H01L21/603 ,  H01L21/302 ,  H01L21/02 ,  H01L29/68

CPC分类号： H01L24/06 ,  H01L21/76865 ,  H01L21/603 ,  H01L21/302 ,  H01L21/02521 ,  H01L21/02123 ,  H01L29/685

摘要： A method for manufacturing a semiconductor device, a first structure is formed on a first substrate. A first bonded body is formed by bonding a supporting substrate lower in rigidity than the first substrate to a first principal surface, on which the first structure is formed, of the first substrate. The first substrate is removed from the first bonded body. A second structure is formed on a second substrate. A third structure is formed on a third substrate. A second bonded body is formed by bonding a second principal surface, on which the second structure is formed, of the second substrate to a third principal surface, on which the third structure is formed, of the third substrate. The second substrate is removed from the second bonded body. A third bonded body is formed by bonding a fourth principal surface, which is exposed after the first substrate is removed, of the first bonded body to a fifth principal surface, which is exposed after the second substrate is removed, of the second bonded body. The supporting substrate is removed from the third bonded body.

公开(公告)号：US10825795B2

公开(公告)日：2020-11-03

申请号：US16427162

申请日：2019-05-30

申请人： Samsung Electronics Co., Ltd.

发明人： Yeong-Seok Kim

IPC分类号： H01L21/00 ,  H01L23/00 ,  H05K3/32 ,  C09J5/06 ,  H01L21/50 ,  H01L21/603 ,  H01L21/60

摘要： A method of manufacturing a semiconductor device may include forming an adhesive film on a surface of a semiconductor chip, mounting the semiconductor chip on a substrate such that the adhesive film contacts an upper surface of the substrate, and bonding the semiconductor chip and the substrate curing the adhesive film by simultaneously performing a thermo-compression process and an ultraviolet irradiation process on the adhesive film disposed between the substrate and the semiconductor chip.

公开(公告)号：US10014283B1

公开(公告)日：2018-07-03

申请号：US15782239

申请日：2017-10-12

申请人： Jing Qiao Corporation Limited

发明人： Chin-Liang Chiang ,  Neng-Huang Chu ,  Yi-Lun Wu

IPC分类号： H01L25/065 ,  H01L23/367 ,  H01L21/48 ,  H01L21/52 ,  H01L21/56 ,  H01L23/495 ,  H01L23/522 ,  H01L23/15 ,  H01L21/60 ,  H01L21/603 ,  H01L25/04 ,  H01L25/11 ,  H01L25/075

CPC分类号： H01L25/0657 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/4882 ,  H01L21/52 ,  H01L21/563 ,  H01L23/13 ,  H01L23/15 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/373 ,  H01L23/4952 ,  H01L23/5226 ,  H01L23/5385 ,  H01L25/043 ,  H01L25/0756 ,  H01L25/117 ,  H01L2021/60022 ,  H01L2021/60277 ,  H01L2021/603 ,  H01L2224/16225

摘要： The present invention provides a semiconductor device including a first glass substrate, a first integrated chip, a first anisotropic conductive film, a second glass substrate, a second integrated chip, a second anisotropic conductive film, and a packaging body.

公开(公告)号：US09799580B2

公开(公告)日：2017-10-24

申请号：US15079276

申请日：2016-03-24

申请人： FREESCALE SEMICONDUCTOR, INC.

发明人： Li Li ,  Jaynal A. Molla ,  Lakshminarayan Viswanathan

IPC分类号： H01L23/34 ,  H01L23/047 ,  H01L21/56 ,  H01L21/52 ,  H01L21/50 ,  H01L23/373 ,  H01L23/00 ,  H01L21/603 ,  H01L21/60

CPC分类号： H01L23/047 ,  H01L21/50 ,  H01L21/52 ,  H01L21/566 ,  H01L23/3157 ,  H01L23/373 ,  H01L23/3736 ,  H01L23/4334 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/75 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L2021/60277 ,  H01L2021/603 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29364 ,  H01L2224/29393 ,  H01L2224/29399 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83193 ,  H01L2224/8384 ,  H01L2224/85439 ,  H01L2224/85455 ,  H01L2224/92247 ,  H01L2924/16195 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/00

摘要： A method of manufacturing a packaged semiconductor device includes forming an assembly by placing a semiconductor die over a substrate with a die attach material between the semiconductor die and the substrate. A conformal structure which includes a pressure transmissive material contacts at least a portion of a top surface of the semiconductor die. A pressure is applied to the conformal structure and in turn, the pressure is transmitted to the top surface of the semiconductor die by the pressure transmissive material. While the pressure is applied, concurrently encapsulating the assembly with a molding compound and exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter.

公开(公告)号：US08940550B1

公开(公告)日：2015-01-27

申请号：US13972981

申请日：2013-08-22

申请人： International Business Machines Corporation

发明人： Benjamin V. Fasano ,  Shidong Li ,  Thomas Weiss

IPC分类号： H01L21/603 ,  H01L23/00 ,  H01L21/48 ,  H01L23/492

CPC分类号： H01L24/11 ,  H01L21/4878 ,  H01L23/492 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/75272 ,  H01L2224/75733 ,  H01L2224/75735 ,  H01L2224/75744 ,  H01L2224/81011 ,  H01L2224/81075 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2224/92125 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/3841 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00014

摘要： Methods for preventing warpage of a laminate may include placing the laminate on a back plate and applying a magnetic force to the laminate to hold the laminate flat against the back plate. In some embodiments, the magnetic force may be applied by placing a first magnet above the laminate so that an attractive force generated between the first magnet and a ferromagnetic region of the back plate pulls the first magnet against the laminate, thereby holding the laminate flat against the back plate. In other embodiments, the magnetic force may be applied by placing a first magnet above the laminate and placing a second magnet above the first magnet so that a repulsive force generated between the first magnet and the magnet pushes the first magnet against the laminate, thereby holding the laminate flat against the back plate.

摘要翻译： 用于防止层压体翘曲的方法可以包括将层压板放置在背板上并向层压板施加磁力，以将层压板平坦地抵靠在背板上。 在一些实施例中，可以通过将第一磁体放置在层压板上方来施加磁力，使得在第一磁体和后板的铁磁区域之间产生的吸引力将第一磁体拉到层压板上，从而将层压板保持抵靠 背板。 在其他实施例中，可以通过将第一磁体放置在层压板上方并将第二磁体放置在第一磁体上方来施加磁力，使得在第一磁体和磁体之间产生的排斥力将第一磁体推到层压板上，从而保持 层压板与背板平齐。

公开(公告)号：US08030135B2

公开(公告)日：2011-10-04

申请号：US12430388

申请日：2009-04-27

申请人： Robert F. Wallace

发明人： Robert F. Wallace

IPC分类号： H01L21/60 ,  H01L21/603

CPC分类号： H01L23/49575 ,  H01L23/4951 ,  H01L23/49537 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/32014 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2225/06572 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： Methods for a multiple die package for integrated circuits are disclosed. An insulator layer is provided and one or more vias are formed within it. The insulator may be provided without vias, and vias formed later. At least one integrated circuit is provided and electrically coupled to at least one lead of a first leadframe overlying one surface of the insulator. At least one second integrated circuit is provided and electrically coupled to a second leadframe overlying a second surface of the insulator. Electrical connections between the two leadframes and the first and second integrated circuits are made through the insulator at selected locations, by coupling at least one lead of the first and second leadframes one to another. The leads of the first and second leadframe may be physically coupled by a welding process within vias in the insulator. A method for a removable storage card is also described.

摘要翻译： 公开了用于集成电路的多管芯封装的方法。 提供绝缘体层，并在其内形成一个或多个通孔。 可以提供绝缘体而没有通孔，并且稍后形成通孔。 至少一个集成电路被提供并且电耦合到覆盖在绝缘体的一个表面上的第一引线框架的至少一个引线。 提供至少一个第二集成电路并且电耦合到覆盖绝缘体的第二表面的第二引线框架。 通过将第一和第二引线框的至少一个引线彼此耦合，在选定位置通过绝缘体制造两个引线框与第一和第二集成电路之间的电连接。 第一引线框架和第二引线框架的引线可以通过在绝缘体中的通孔内的焊接工艺物理耦合。 还描述了用于可移动存储卡的方法。

公开(公告)号：US20110227223A1

公开(公告)日：2011-09-22

申请号：US13049550

申请日：2011-03-16

申请人： Albert Wu ,  Scott Wu

发明人： Albert Wu ,  Scott Wu

IPC分类号： H01L23/498 ,  H01L21/603

CPC分类号： H01L24/82 ,  H01L23/3121 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/24226 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/3512 ,  H01L2924/00

摘要： Embodiments of the present disclosure provide a substrate having (i) a first laminate layer, (ii) a second laminate layer, and (iii) a core material that is disposed between the first laminate layer and the second laminate layer; and a die attached to the first laminate layer, the die having an interposer bonded to a surface of an active side of the die, the surface comprising (i) a dielectric material and (ii) a bond pad to route electrical signals of the die, the interposer having a via formed therein, the via being electrically coupled to the bond pad to further route the electrical signals of the die, wherein the die and the interposer are embedded in the core material of the substrate. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例提供一种基板，其具有（i）第一层叠层，（ii）第二层叠层，以及（iii）设置在第一层叠层和第二层叠层之间的芯材料; 和模具，其附接到第一层压层，所述模具具有接合到所述管芯的有效侧的表面的插入件，所述表面包括（i）电介质材料和（ii）用于引导所述管芯的电信号的接合焊盘 所述插入件具有形成在其中的通孔，所述通孔电耦合到所述接合焊盘，以进一步布置所述管芯的电信号，其中所述管芯和所述插入件嵌入在所述衬底的芯材中。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20110079916A1

公开(公告)日：2011-04-07

申请号：US12572615

申请日：2009-10-02

申请人： JEFFREY A. WEST

发明人： JEFFREY A. WEST

IPC分类号： H01L23/488 ,  H01L21/603

CPC分类号： H01L24/13 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/13011 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13611 ,  H01L2224/1403 ,  H01L2224/16 ,  H01L2224/16105 ,  H01L2224/29 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/29298 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/81136 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/812 ,  H01L2224/81201 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2224/81898 ,  H01L2224/83194 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/01047 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929 ,  H01L2924/00012

摘要： An electronic assembly includes an IC die including a semiconductor top surface having active circuitry thereon and a bottom surface, and at least one protruding bonding feature having sidewall surfaces and a leading edge surface extending outward from the IC die. A workpiece has a workpiece surface including at least one electrical connector and at least one framed hollow receptacle coupled to the electrical connector. The receptacle is formed from metal and includes sidewall portions and a bent top that defines a cavity. The bent top includes bent peripheral shelf regions that point downward into the cavity and towards the sidewall portions. The protruding bonding feature is inserted within the cavity of the receptacle and contacts the bent peripheral shelf regions along a contact area to form a metallic joint, wherein the contact area is at least primarily along the sidewall surfaces.

摘要翻译： 电子组件包括IC芯片，IC芯片包括其上具有有源电路的半导体顶表面和底表面，以及具有侧壁表面的至少一个突出接合特征以及从IC芯片向外延伸的前缘表面。 工件具有包括至少一个电连接器和耦合到电连接器的至少一个框架式中空插座的工件表面。 容器由金属形成并且包括侧壁部分和限定空腔的弯曲顶部。 弯曲的顶部包括弯曲的外围搁板区域，其向下指向空腔并朝向侧壁部分。 突出接合特征被插入到容器的空腔内并且沿着接触区域接触弯曲的外围搁架区域以形成金属接头，其中接触区域至少主要沿侧壁表面。

公开(公告)号：US07713782B2

公开(公告)日：2010-05-11

申请号：US11525493

申请日：2006-09-22

申请人： Rajendra D. Pendse

发明人： Rajendra D. Pendse

IPC分类号： H01L21/603

CPC分类号： H01L24/16 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/81 ,  H01L27/14618 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05624 ,  H01L2224/1134 ,  H01L2224/16 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48624 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/48824 ,  H01L2924/00 ,  H01L2924/01049

摘要： Methods are disclosed for electrically connecting I/O bond-pads on a chip to corresponding I/O bond-pads on a substrate. In an exemplary method a respective stud-bump is formed on each I/O bond-pad on the substrate. The stud-bumps can be made of a fusible material, or a layer of fusible material can be formed on each I/O bond-pad on the chip. The chip is flipped and placed on the stud-bumps such that the I/O bond-pads on the chip are registered with the corresponding stud-bumps on the substrate. At each stud-bump, the fusible material is caused to fuse with and electrically connect the respective stud-bump to the respective I/O bond-pad on the chip. The method can include forming under-bump metallization (UBM) on each of the I/O bond-pads on the chip before placing the chip on the stud-bumps. The resulting structures provide robust I/O connections and can be fabricated using fewer process steps and using process steps that are compatible with other processes in wafer-fabrication and chip-assembly facilities.

摘要翻译： 公开了用于将芯片上的I / O接合焊盘电连接到衬底上相应的I / O焊盘的方法。 在示例性方法中，在基板上的每个I / O接合焊盘上形成相应的柱形凸块。 螺柱凸起可以由可熔材料制成，或者可以在芯片上的每个I / O焊盘上形成一层易熔材料。 芯片被翻转并放置在柱状凸块上，使得芯片上的I / O接合焊盘与衬底上的相应的柱形凸块对准。 在每个螺柱凸块处，引起可熔材料与相应的凸块凸起熔合并将其电连接到芯片上相应的I / O焊盘。 该方法可以包括在将芯片放置在螺柱凸起之前在芯片上的每个I / O焊盘上形成凸块下金属化（UBM）。 所得到的结构提供强大的I / O连接，并且可以使用较少的工艺步骤和使用与晶片制造和芯片组装设备中的其他工艺兼容的工艺步骤来制造。