公开(公告)号：US20180138269A1

公开(公告)日：2018-05-17

申请号：US15715832

申请日：2017-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok Hoon KIM ,  Hyun Jung LEE ,  Kyung Hee KIM ,  Sun Jung KIM ,  Jin Bum KIM ,  Il Gyou SHIN ,  Seung Hun LEE ,  Cho Eun LEE ,  Dong Suk SHIN

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L21/0257 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: There is provided a semiconductor device capable of enhancing short channel effect by forming a carbon-containing semiconductor pattern in a source/drain region. The semiconductor device includes a first gate electrode and a second gate electrode spaced apart from each other on a fin-type pattern, a recess formed in the fin-type pattern between the first gate electrode and the second gate electrode, and a semiconductor pattern including a lower semiconductor film formed along a profile of the recess and an upper semiconductor film on the lower semiconductor film, wherein the lower semiconductor film includes a lower epitaxial layer and an upper epitaxial layer sequentially formed on the fin-type pattern, and a carbon concentration of the upper epitaxial layer is greater than a carbon concentration of the lower epitaxial layer.

公开(公告)号：US20180114791A1

公开(公告)日：2018-04-26

申请号：US15850183

申请日：2017-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Hwan KIM ,  Gi Gwan PARK ,  Jung Gun YOU ,  Dong Suk SHIN ,  Hyun Yul CHOI

IPC: H01L27/092 ,  H01L21/84 ,  H01L27/02 ,  H01L27/088 ,  H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/167 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41766 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate comprising first and second regions, in the first region, first and second gate electrodes formed parallel to each other on the substrate, and being spaced apart from each other by a first distance, in the second region, third and fourth gate electrodes formed parallel to each other on the substrate, and being spaced apart from each other by a second distance which is greater than the first distance, in the first region, a first recess formed on the substrate between the first and second gate electrodes, in the second region, a second recess formed on the substrate between the third and fourth gate electrodes, a first epitaxial source/drain filling the first recess and a second epitaxial source/drain filling the second recess, wherein an uppermost portion of an upper surface of the first epitaxial source/drain is higher than an uppermost portion of an upper surface of the second epitaxial source/drain.

公开(公告)号：US20180096845A1

公开(公告)日：2018-04-05

申请号：US15595945

申请日：2017-05-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cho Eun LEE ,  Jin Bum KIM ,  Kang Hun MOON ,  Jae Myung CHOE ,  Sun Jung KIM ,  Dong Suk SHIN ,  IL GYOU SHIN ,  Jeong Ho YOO

IPC: H01L21/02 ,  H01L21/223 ,  H01L29/66

CPC classification number: H01L21/02661 ,  H01L21/02071 ,  H01L21/223 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795

Abstract: A method of fabricating a semiconductor device is provided. The method includes forming a dummy gate electrode on a substrate, forming a trench on a side surface of the dummy gate electrode, performing a bake process of removing an impurity from the trench and forming a source/drain in the trench, wherein the bake process comprises a first stage and a second stage following the first stage, an air pressure in which the substrate is disposed during the first stage is different from an air pressure in which the substrate is disposed during the second stage, and the bake process is performed while the substrate is on a stage rotating the substrate, wherein a revolution per minute (RPM) of the substrate during the first stage is different from a revolution per minute (RPM) of the substrate during the second stage.

公开(公告)号：US20240194786A1

公开(公告)日：2024-06-13

申请号：US18531898

申请日：2023-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Suk SHIN ,  Jung Taek KIM ,  Hyun-Kwan YU ,  Seok Hoon KIM ,  Pan Kwi PARK ,  Seo Jin JEONG ,  Nam Kyu CHO

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/7855 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/66545

Abstract: There is provided a semiconductor device capable of improving performance and reliability of an element. The semiconductor device includes an active pattern extending in a first direction, and a plurality of gate structures spaced apart from each other in the first direction on the active pattern. Each gate structure comprises a gate electrode extending in a second direction and a gate spacer on a sidewall of the gate electrode and a source/drain pattern disposed between adjacent gate structures. The gate structure comprises a semiconductor liner layer and a semiconductor filling layer on the semiconductor liner layer, wherein the semiconductor liner layer and the semiconductor filling layer are formed of silicon-germanium. The semiconductor filling layer comprises an upper portion protruding in a third direction beyond an upper surface of the active pattern. A maximum width of the upper portion of the semiconductor filling layer in the first direction is greater than a width of the semiconductor filling layer in the first direction on the upper surface of the active pattern. The semiconductor liner layer comprises an outer surface in contact with the active pattern and an inner surface facing the semiconductor filling layer. In a plan view, the inner surface of the semiconductor liner layer comprises a concave region.

公开(公告)号：US20180130886A1

公开(公告)日：2018-05-10

申请号：US15685255

申请日：2017-08-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin Bum KIM ,  Gyeom KIM ,  Seok Hoon KIM ,  Tae Jin PARK ,  Jeong Ho YOO ,  Cho Eun LEE ,  Hyun Jung LEE ,  Sun Jung KIM ,  Dong Suk SHIN

IPC: H01L29/417 ,  H01L27/092 ,  H01L29/51 ,  H01L29/423 ,  H01L21/02 ,  H01L21/3205

CPC classification number: H01L29/41725 ,  H01L21/02425 ,  H01L21/32053 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/42356 ,  H01L29/517 ,  H01L2924/0002

Abstract: A semiconductor device includes: a substrate having an active region; a gate structure disposed in the active region; source/drain regions respectively formed within portions of the active region disposed on both sides of the gate structure; a metal silicide layer disposed on a surface of each of the source/drain regions; and contact plugs disposed on the source/drain regions and electrically connected to the source/drain regions through the metal silicide layer, respectively. The metal silicide layer is formed so as to have a monocrystalline structure.

公开(公告)号：US20230056095A1

公开(公告)日：2023-02-23

申请号：US17734564

申请日：2022-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nam Kyu CHO ,  Sang Gil LEE ,  Seok Hoon KIM ,  Yong Seung KIM ,  Jung Taek KIM ,  Pan Kwi PARK ,  Dong Suk SHIN ,  Si Hyung LEE ,  Yang XU

IPC: H01L29/778 ,  H01L29/78 ,  H01L29/423

Abstract: A semiconductor device includes a substrate including a first region and a second region, a first active pattern on the first region, a first gate structure having a first width in the first direction, on the first active pattern, a first epitaxial pattern disposed in the first active pattern on a side surface of the first gate structure, a second active pattern on the second region, a second gate structure having a second width greater than the first width in the first direction, on the second active pattern and a second epitaxial pattern disposed in the second active pattern on a side surface of the second gate structure. Each of the first epitaxial pattern and the second epitaxial pattern includes silicon germanium (SiGe), and a first Ge concentration of the first epitaxial pattern is lower than a second Ge concentration of the second epitaxial pattern.

公开(公告)号：US20190058051A1

公开(公告)日：2019-02-21

申请号：US15896277

申请日：2018-02-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin Bum KIM ,  Tae Jin PARK ,  Jong Min LEE ,  Seok Hoon KIM ,  Dong Chan SUH ,  Jeong Ho YOO ,  Ha Kyu SEONG ,  Dong Suk SHIN

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/40

Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the semiconductor device including a channel pattern on a substrate, the channel pattern extending in a first direction; a gate pattern on the substrate, the gate pattern extending in a second direction crossing the first direction and surrounding the channel pattern; and an interface layer between the channel pattern and the gate pattern, the interface layer being formed on at least one surface of an upper surface and a lower surface of the channel pattern.

公开(公告)号：US20170162576A1

公开(公告)日：2017-06-08

申请号：US15368723

申请日：2016-12-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Hwan KIM ,  Gi Gwan PARK ,  Jung Gun YOU ,  Dong Suk SHIN ,  Hyun Yul CHOI

IPC: H01L27/092 ,  H01L29/08 ,  H01L29/417 ,  H01L29/45 ,  H01L29/167 ,  H01L29/165 ,  H01L29/06 ,  H01L29/78 ,  H01L27/02

CPC classification number: H01L27/0924 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41766 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate comprising first and second regions, in the first region, first and second gate electrodes formed parallel to each other on the substrate, and being spaced apart from each other by a first distance, in the second region, third and fourth gate electrodes formed parallel to each other on the substrate, and being spaced apart from each other by a second distance which is greater than the first distance, in the first region, a first recess formed on the substrate between the first and second gate electrodes, in the second region, a second recess formed on the substrate between the third and fourth gate electrodes, a first epitaxial source/drain filling the first recess and a second epitaxial source/drain filling the second recess, wherein an uppermost portion of an upper surface of the first epitaxial source/drain is higher than an uppermost portion of an upper surface of the second epitaxial source/drain.

公开(公告)号：US20190207008A1

公开(公告)日：2019-07-04

申请号：US16294158

申请日：2019-03-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun Kwan YU ,  Kyung Ho KIM ,  Dong Suk SHIN

IPC: H01L29/49 ,  H01L21/8234 ,  H01L29/165 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66 ,  H01L29/16 ,  H01L29/161 ,  H01L29/08 ,  H01L29/06 ,  H01L27/11 ,  H01L27/088

CPC classification number: H01L29/4983 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device includes a field insulating film including a first region and a second region on a substrate, a recess in the first region of the field insulating film, a gate electrode on the second region of the field insulating film, and a gate spacer along a sidewall of the gate electrode and a sidewall of the recess.

公开(公告)号：US20240332424A1

公开(公告)日：2024-10-03

申请号：US18740736

申请日：2024-06-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yang XU ,  Nam Kyu CHO ,  Seok Hoon KIM ,  Yong Seung KIM ,  Pan Kwi PARK ,  Dong Suk SHIN ,  Sang Gil LEE ,  Si Hyung LEE

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L29/7851 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/41791

Abstract: A semiconductor device including first fin-shaped patterns in a first region of a substrate and spaced apart from each other in a first direction, second fin-shaped patterns in a second region of the substrate and spaced apart from each other in a second direction, a first field insulating film on the substrate and covering sidewalls of the first fin-shaped patterns, a second field insulating film on the substrate and covering sidewalls of the second fin-shaped patterns, a first source/drain pattern on the first field insulating film, connected to the first fin-shaped patterns, and including a first silicon-germanium pattern, and a second source/drain pattern on the second field insulating film, connected to the second fin-shaped patterns, and including a second silicon-germanium pattern, the second source/drain pattern and the second field insulating film defining one or more first air gaps therebetween may be provided.