公开(公告)号：US20180151705A1

公开(公告)日：2018-05-31

申请号：US15871479

申请日：2018-01-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： JinBum KIM ,  Kang Hun MOON ,  Choeun LEE ,  Sujin JUNG ,  Yang XU

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/823425 ,  H01L21/823431 ,  H01L29/0657 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7848

Abstract: Methods of forming an integrated circuit device are provided. The methods may include forming a gate structure on a substrate, forming a first etch mask on a sidewall of the gate structure, anisotropically etching the substrate using the gate structure and the first etch mask as an etch mask to form a preliminary recess in the substrate, forming a sacrificial layer in the preliminary recess, forming a second etch mask on the first etch mask, etching the sacrificial layer and the substrate beneath the sacrificial layer using the gate structure and the first and second etch masks as an etch mask to form a source/drain recess in the substrate, and forming a source/drain in the source/drain recess. A sidewall of the source/drain recess may be recessed toward the gate structure relative to an outer surface of the second etch mask.

公开(公告)号：US20230056095A1

公开(公告)日：2023-02-23

申请号：US17734564

申请日：2022-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nam Kyu CHO ,  Sang Gil LEE ,  Seok Hoon KIM ,  Yong Seung KIM ,  Jung Taek KIM ,  Pan Kwi PARK ,  Dong Suk SHIN ,  Si Hyung LEE ,  Yang XU

IPC: H01L29/778 ,  H01L29/78 ,  H01L29/423

Abstract: A semiconductor device includes a substrate including a first region and a second region, a first active pattern on the first region, a first gate structure having a first width in the first direction, on the first active pattern, a first epitaxial pattern disposed in the first active pattern on a side surface of the first gate structure, a second active pattern on the second region, a second gate structure having a second width greater than the first width in the first direction, on the second active pattern and a second epitaxial pattern disposed in the second active pattern on a side surface of the second gate structure. Each of the first epitaxial pattern and the second epitaxial pattern includes silicon germanium (SiGe), and a first Ge concentration of the first epitaxial pattern is lower than a second Ge concentration of the second epitaxial pattern.

公开(公告)号：US20220130982A1

公开(公告)日：2022-04-28

申请号：US17571694

申请日：2022-01-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun Kwan YU ,  Seung Hun LEE ,  Yang XU

IPC: H01L29/66 ,  H01L29/165 ,  H01L29/201 ,  H01L29/20

Abstract: A method of manufacturing a semiconductor device, the method including: forming, in a first region of a substrate, an active fin and a sacrificial gate structure intersecting the active fin; forming a first spacer and a second spacer on the substrate to cover the sacrificial gate structure; forming a mask in a second region of the substrate to expose the first region of the substrate; removing the second spacer from the first spacer in the first region of the substrate by using the mask; forming recesses at opposite sides of the sacrificial gate structure by removing portions of the active fin; forming a source and a drain in the recesses; and forming an etch-stop layer to cover both sidewalls of the sacrificial gate structure and a top surfaces of the source and drain.

公开(公告)号：US20240405113A1

公开(公告)日：2024-12-05

申请号：US18537916

申请日：2023-12-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yang XU ,  Gyeom KIM ,  Young Kwang KIM ,  Jin Bum KIM ,  Yoon Tae NAM ,  Kyung Bin CHUN ,  Ryong HA ,  Yoon HEO

IPC: H01L29/775 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device includes a substrate. An active pattern extends in a first horizontal direction on the substrate. First to third nanosheets are sequentially spaced apart from each other in a vertical direction on the active pattern. A gate electrode extends in a second horizontal direction on the active pattern and surrounds the first to third nanosheets. A source/drain region includes a first layer disposed along side walls and a bottom surface of a source/drain trench and a second layer filling the source/drain trench. The second layer includes a first lower side wall facing a side wall of the first nanosheet and an opposite second lower side wall. A lower surface connects the first and second lower side walls and extends in the first horizontal direction. The first and second lower side walls of the second layer extend to have a constant slope in opposite directions to each other.

公开(公告)号：US20190139811A1

公开(公告)日：2019-05-09

申请号：US15869718

申请日：2018-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunguk Jang ,  Seokhoon KIM ,  Seung Hun LEE ,  Yang XU ,  Jeongho YOO ,  Jongryeol YOO ,  Youngdae CHO

IPC: H01L21/762 ,  H01L29/66 ,  H01L29/423 ,  H01L29/165 ,  H01L21/02 ,  H01L21/225

Abstract: Semiconductor devices and methods of forming the same are provided. The methods may implanting dopants into a substrate to form a preliminary impurity region and heating the substrate to convert the preliminary impurity region into an impurity region. Heating the substrate may be performed at an ambient temperature of from about 800° C. to about 950° C. for from about 20 min to about 50 min. The method may also include forming first and second trenches in the impurity region to define an active tin and forming a first isolation layer and a second isolation layer in the first and second trenches, respectively. The first and second isolation layers may expose opposing sides of the active fin. The method may further include forming a gate insulation layer extending on the opposing sides and an upper surface of the active fin and forming a gate electrode traversing the active fin

公开(公告)号：US20180108779A1

公开(公告)日：2018-04-19

申请号：US15844863

申请日：2017-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sujin JUNG ,  JinBum KIM ,  KANG HUN MOON ,  KWAN HEUM LEE ,  BYEONGCHAN LEE ,  Choeun LEE ,  Yang XU

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/7848

Abstract: A semiconductor device is disclosed. The device includes a substrate including an active region defined by a device isolation layer, a fin pattern protruding from the substrate and extending in a first direction, the fin pattern including a gate fin region and a source/drain fin region, a gate pattern disposed on the gate fin region to extend in a second direction crossing the first direction, and a source/drain portion provided on a sidewall of the source/drain fin region. When measured in the second direction, a width of the source/drain fin region is different from a width in the second direction of the gate fin region.

公开(公告)号：US20170148797A1

公开(公告)日：2017-05-25

申请号：US15351739

申请日：2016-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Bum KIM ,  Myung-Gil KANG ,  Kang-Hun MOON ,  Cho-Eun LEE ,  Su-Jin JUNG ,  Min-Hee CHOI ,  Yang XU ,  Dong-Suk SHIN ,  Kwan-Heum LEE ,  Hoi-Sung CHUNG

IPC: H01L27/11 ,  H01L29/45 ,  H01L29/161 ,  H01L23/528 ,  H01L27/088 ,  H01L29/08

CPC classification number: H01L27/1104 ,  H01L21/823431 ,  H01L23/485 ,  H01L23/5283 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/66545 ,  H01L29/7848

Abstract: A semiconductor device may include a first active fin, a plurality of second active fins, a first source/drain layer structure, and a second source/drain layer structure. The first active fin may be on a first region of a substrate. The second active fins may be on a second region of the substrate. The first and second gate structures may be on the first and second active fins, respectively. The first source/drain layer structure may be on a portion of the first active fin that is adjacent to the first gate structure. The second source/drain layer structure may commonly contact upper surfaces of the second active fins adjacent to the second gate structure. A top surface of the second source/drain layer structure may be further from the surface of the substrate than a top surface of the first source/drain layer structure is to the surface of the substrate.

公开(公告)号：US20160351715A1

公开(公告)日：2016-12-01

申请号：US15135566

申请日：2016-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sujin JUNG ,  JinBum KIM ,  KANG HUN MOON ,  KWAN HEUM LEE ,  BYEONGCHAN LEE ,  Choeun LEE ,  Yang XU

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08

CPC classification number: H01L29/7851 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/7848

Abstract: A semiconductor device is disclosed. The device includes a substrate including an active region defined by a device isolation layer, a fin pattern protruding from the substrate and extending in a first direction, the fin pattern including a gate fin region and a source/drain fin region, a gate pattern disposed on the gate fin region to extend in a second direction crossing the first direction, and a source/drain portion provided on a sidewall of the source/drain fin region. When measured in the second direction, a width of the source/drain fin region is different from a width in the second direction of the gate fin region.

Abstract translation: 公开了一种半导体器件。 该器件包括：衬底，其包括由器件隔离层限定的有源区，从衬底突出并沿第一方向延伸的鳍状图案，所述鳍图案包括栅极鳍区和源极/漏极鳍区，栅极图案设置 在所述栅极鳍区域上沿与所述第一方向交叉的第二方向延伸，以及设置在所述源极/漏极鳍片区域的侧壁上的源极/漏极部分。 当在第二方向上测量时，源极/漏极鳍片区域的宽度不同于栅极鳍片区域的第二方向上的宽度。

公开(公告)号：US20240332424A1

公开(公告)日：2024-10-03

申请号：US18740736

申请日：2024-06-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yang XU ,  Nam Kyu CHO ,  Seok Hoon KIM ,  Yong Seung KIM ,  Pan Kwi PARK ,  Dong Suk SHIN ,  Sang Gil LEE ,  Si Hyung LEE

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L29/7851 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/41791

Abstract: A semiconductor device including first fin-shaped patterns in a first region of a substrate and spaced apart from each other in a first direction, second fin-shaped patterns in a second region of the substrate and spaced apart from each other in a second direction, a first field insulating film on the substrate and covering sidewalls of the first fin-shaped patterns, a second field insulating film on the substrate and covering sidewalls of the second fin-shaped patterns, a first source/drain pattern on the first field insulating film, connected to the first fin-shaped patterns, and including a first silicon-germanium pattern, and a second source/drain pattern on the second field insulating film, connected to the second fin-shaped patterns, and including a second silicon-germanium pattern, the second source/drain pattern and the second field insulating film defining one or more first air gaps therebetween may be provided.

公开(公告)号：US20230058991A1

公开(公告)日：2023-02-23

申请号：US17690178

申请日：2022-03-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yang XU ,  Nam Kyu CHO ,  Seok Hoon KIM ,  Yong Seung KIM ,  Pan Kwi PARK ,  Dong Suk SHIN ,  Sang Gil LEE ,  Si Hyung LEE

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/417 ,  H01L29/06

Abstract: A semiconductor device including first fin-shaped patterns in a first region of a substrate and spaced apart from each other in a first direction, second fin-shaped patterns in a second region of the substrate and spaced apart from each other in a second direction, a first field insulating film on the substrate and covering sidewalls of the first fin-shaped patterns, a second field insulating film on the substrate and covering sidewalls of the second fin-shaped patterns, a first source/drain pattern on the first field insulating film, connected to the first fin-shaped patterns, and including a first silicon-germanium pattern, and a second source/drain pattern on the second field insulating film, connected to the second fin-shaped patterns, and including a second silicon-germanium pattern, the second source/drain pattern and the second field insulating film defining one or more first air gaps therebetween may be provided.