公开(公告)号：US20220173253A1

公开(公告)日：2022-06-02

申请号：US17327725

申请日：2021-05-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DONGHYUK YEOM ,  JUNKYUM KIM ,  KWAN HEUM LEE ,  SEONGHWA PARK ,  SOHYUN SEO

IPC: H01L29/786 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: A semiconductor device includes; an active pattern on a substrate, a source/drain pattern on the active pattern, a channel pattern connected to the source/drain pattern and including semiconductor patterns spaced apart in a vertical stack, and a gate electrode extending across the channel pattern. The semiconductor patterns includes a first semiconductor pattern and a second semiconductor pattern. The gate electrode includes a first part between the substrate and the first semiconductor pattern and a second part between the first semiconductor pattern and the second semiconductor pattern. A width of the first part varies with a depth of the first part, such that a width of a middle portion of the first part is less than a width of a lower portion of the first part and a width of an upper portion of the first part.

公开(公告)号：US20150206955A1

公开(公告)日：2015-07-23

申请号：US14498996

申请日：2014-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： JinBum KIM ,  Seong Hoon JEONG ,  JEON IL LEE ,  SEOKHOON KIM ,  KWAN HEUM LEE ,  Choeun LEE ,  Yu-Jin PYO

IPC: H01L29/66 ,  H01L29/161 ,  H01L21/02 ,  H01L29/51

CPC classification number: H01L29/66795 ,  H01L21/0223 ,  H01L21/02252 ,  H01L21/02326 ,  H01L21/0234 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/1211 ,  H01L29/161 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

Abstract: The inventive concepts provide methods of manufacturing a semiconductor device. The method includes patterning a substrate to form an active pattern, forming a gate pattern intersecting the active pattern, forming a gate spacer on a sidewall of the gate pattern, forming a growth-inhibiting layer covering an upper region of the gate pattern, and forming source/drain electrodes at opposite first and second sides of the gate pattern.

Abstract translation: 本发明构思提供制造半导体器件的方法。 该方法包括图案化衬底以形成有源图案，形成与有源图案相交的栅极图案，在栅极图案的侧壁上形成栅极间隔物，形成覆盖栅极图案的上部区域的生长抑制层，以及形成 源极/漏极在栅极图案的相对的第一和第二侧。

公开(公告)号：US20180108779A1

公开(公告)日：2018-04-19

申请号：US15844863

申请日：2017-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sujin JUNG ,  JinBum KIM ,  KANG HUN MOON ,  KWAN HEUM LEE ,  BYEONGCHAN LEE ,  Choeun LEE ,  Yang XU

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/7848

Abstract: A semiconductor device is disclosed. The device includes a substrate including an active region defined by a device isolation layer, a fin pattern protruding from the substrate and extending in a first direction, the fin pattern including a gate fin region and a source/drain fin region, a gate pattern disposed on the gate fin region to extend in a second direction crossing the first direction, and a source/drain portion provided on a sidewall of the source/drain fin region. When measured in the second direction, a width of the source/drain fin region is different from a width in the second direction of the gate fin region.

公开(公告)号：US20160351715A1

公开(公告)日：2016-12-01

申请号：US15135566

申请日：2016-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sujin JUNG ,  JinBum KIM ,  KANG HUN MOON ,  KWAN HEUM LEE ,  BYEONGCHAN LEE ,  Choeun LEE ,  Yang XU

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08

CPC classification number: H01L29/7851 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/7848

Abstract: A semiconductor device is disclosed. The device includes a substrate including an active region defined by a device isolation layer, a fin pattern protruding from the substrate and extending in a first direction, the fin pattern including a gate fin region and a source/drain fin region, a gate pattern disposed on the gate fin region to extend in a second direction crossing the first direction, and a source/drain portion provided on a sidewall of the source/drain fin region. When measured in the second direction, a width of the source/drain fin region is different from a width in the second direction of the gate fin region.

Abstract translation: 公开了一种半导体器件。 该器件包括：衬底，其包括由器件隔离层限定的有源区，从衬底突出并沿第一方向延伸的鳍状图案，所述鳍图案包括栅极鳍区和源极/漏极鳍区，栅极图案设置 在所述栅极鳍区域上沿与所述第一方向交叉的第二方向延伸，以及设置在所述源极/漏极鳍片区域的侧壁上的源极/漏极部分。 当在第二方向上测量时，源极/漏极鳍片区域的宽度不同于栅极鳍片区域的第二方向上的宽度。

公开(公告)号：US20150287711A1

公开(公告)日：2015-10-08

申请号：US14562788

申请日：2014-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： SEOKHOON KIM ,  BONYOUNG KOO ,  JinBum KIM ,  CHUL KIM ,  KWAN HEUM LEE ,  BYEONGCHAN LEE ,  Sujin JUNG

IPC: H01L27/02 ,  H01L29/06 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L27/0207 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/7834 ,  H01L29/7848

Abstract: Provided is a semiconductor device which includes a substrate including a first region and a second region different from the first region, a first active pattern provided on the substrate in the first region, a second active pattern provided on the substrate in the second region, a first gate structure crossing over the first active pattern and a second gate structure crossing over the second active pattern, first source/drain regions disposed on the first active pattern at opposite sides of the first gate structure, second source/drain regions disposed on the second active pattern at opposite sides of the second gate structure, and auxiliary spacers disposed in the first region to cover a lower portion of each of the first source/drain regions.

Abstract translation: 提供一种半导体器件，其包括：衬底，其包括第一区域和与第一区域不同的第二区域;设置在第一区域中的衬底上的第一有源图案，设置在第二区域中的衬底上的第二有源图案; 在第一有源图案上交叉的第一栅极结构和与第二有源图案交叉的第二栅极结构，在第一栅极结构的相对侧设置在第一有源图案上的第一源/漏区，设置在第二有源图案上的第二栅极结构的第二栅极结构 在第二栅极结构的相对侧的有源图案以及设置在第一区域中以覆盖每个第一源极/漏极区域的下部的辅助间隔物。

公开(公告)号：US20230019278A1

公开(公告)日：2023-01-19

申请号：US17673880

申请日：2022-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： DONGHYUK YEOM ,  KWAN HEUM LEE ,  SEONGHWA PARK ,  SECHAN LIM

IPC: H01L29/786 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device includes an active pattern on a substrate, a device isolation layer provided on the substrate to define the active pattern, a pair of source/drain patterns on the active pattern and a channel pattern therebetween, the channel pattern including semiconductor patterns which are stacked and are spaced apart from each other, a gate electrode crossing the channel pattern, and a gate spacer on a side surface of the gate electrode. The gate spacer located on the device isolation layer includes an upper portion with a first thickness and a lower portion with a second thickness. The second thickness is larger than the first thickness, and the lower portion of the gate spacer is located at a level lower than the uppermost one of the semiconductor patterns.

公开(公告)号：US20170271479A1

公开(公告)日：2017-09-21

申请号：US15612338

申请日：2017-06-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JINBUM KIM ,  JAEYOUNG PARK ,  DONGHUN LEE ,  JEONGHO YOO ,  JIEON YOON ,  KWAN HEUM LEE ,  CHOEUN LEE ,  BONYOUNG KOO

IPC: H01L29/66 ,  H01L29/12 ,  H01L29/417 ,  H01L29/423 ,  H01L29/40 ,  H01L21/30 ,  H01L29/78 ,  H01L29/08 ,  H01L29/04 ,  H01L29/165

CPC classification number: H01L29/66636 ,  H01L21/3003 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/12 ,  H01L29/165 ,  H01L29/401 ,  H01L29/41766 ,  H01L29/42356 ,  H01L29/66545 ,  H01L29/78

Abstract: A method of fabricating a semiconductor device is provided as follows. A source/drain pattern is formed on a substrate. The source/drain pattern contains silicon atoms and germanium atoms. At least one germanium atom is removed from the germanium atoms of the source/drain pattern.

公开(公告)号：US20160087104A1

公开(公告)日：2016-03-24

申请号：US14861748

申请日：2015-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： BYEONGCHAN LEE ,  Nam-Kyu KIM ,  JinBum KIM ,  KWAN HEUM LEE ,  Choeun LEE ,  Sujin JUNG

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/7851 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848

Abstract: Provided are a semiconductor device and a method of fabricating the same. The device may include an active pattern protruding from a substrate, gate structures crossing the active pattern, and a source/drain region provided between adjacent ones of the gate structures. The source/drain region may include a source/drain epitaxial layer in a recessed region, which is formed in the active pattern between the adjacent ones of the gate structures. Further, an impurity diffusion region may be provided in the active pattern to enclose the source/drain epitaxial layer along inner surfaces of the recessed region.

Abstract translation: 提供半导体器件及其制造方法。 器件可以包括从衬底突出的有源图案，与有源图案交叉的栅极结构以及设置在相邻栅极结构之间的源极/漏极区域。 源极/漏极区域可以包括凹陷区域中的源极/漏极外延层，其形成在相邻的栅极结构之间的有源图案中。 此外，可以在有源图案中提供杂质扩散区域以沿着凹陷区域的内表面包围源极/漏极外延层。