公开(公告)号：US20150206956A1

公开(公告)日：2015-07-23

申请号：US14499922

申请日：2014-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： JinBum KIM ,  JUNGHO YOO ,  BYEONGCHAN LEE ,  Choeun LEE ,  HYUN JUNG LEE ,  Seong Hoon JEONG ,  BONYOUNG KOO

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/165 ,  H01L21/8234

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823481 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7848

Abstract: A method of manufacturing a semiconductor device includes forming an active pattern protruding from a semiconductor substrate, forming a dummy gate pattern crossing over the active pattern, forming gate spacers on opposite first and second sidewalls of the dummy gate pattern, removing the dummy gate pattern to form a gate region exposing an upper surface and sidewalls of the active pattern between the gate spacers, recessing the upper surface of the active pattern exposed by the gate region to form a channel recess region, forming a channel pattern in the channel recess region by a selective epitaxial growth (SEG) process, and sequentially forming a gate dielectric layer and a gate electrode covering an upper surface and sidewalls of the channel pattern in the gate region. The channel pattern has a lattice constant different from that of the semiconductor substrate.

Abstract translation: 一种制造半导体器件的方法包括形成从半导体衬底突出的有源图案，形成与有源图案交叉的伪栅极图案，在伪栅极图案的相对的第一和第二侧壁上形成栅极间隔物，将伪栅极图案去除 形成栅极区域，暴露栅极间隔件之间的有源图案的上表面和侧壁，凹陷由栅极区域暴露的有源图案的上表面，以形成通道凹槽区域，在通道凹槽区域中形成通道图案 选择性外延生长（SEG）工艺，以及顺序地形成覆盖栅极区域中的沟道图案的上表面和侧壁的栅极电介质层和栅电极。 沟道图案具有与半导体衬底不同的晶格常数。

公开(公告)号：US20160087104A1

公开(公告)日：2016-03-24

申请号：US14861748

申请日：2015-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： BYEONGCHAN LEE ,  Nam-Kyu KIM ,  JinBum KIM ,  KWAN HEUM LEE ,  Choeun LEE ,  Sujin JUNG

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/7851 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848

Abstract: Provided are a semiconductor device and a method of fabricating the same. The device may include an active pattern protruding from a substrate, gate structures crossing the active pattern, and a source/drain region provided between adjacent ones of the gate structures. The source/drain region may include a source/drain epitaxial layer in a recessed region, which is formed in the active pattern between the adjacent ones of the gate structures. Further, an impurity diffusion region may be provided in the active pattern to enclose the source/drain epitaxial layer along inner surfaces of the recessed region.

Abstract translation: 提供半导体器件及其制造方法。 器件可以包括从衬底突出的有源图案，与有源图案交叉的栅极结构以及设置在相邻栅极结构之间的源极/漏极区域。 源极/漏极区域可以包括凹陷区域中的源极/漏极外延层，其形成在相邻的栅极结构之间的有源图案中。 此外，可以在有源图案中提供杂质扩散区域以沿着凹陷区域的内表面包围源极/漏极外延层。

公开(公告)号：US20150380553A1

公开(公告)日：2015-12-31

申请号：US14673519

申请日：2015-03-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KEUM SEOK PARK ,  JUNGHO YOO ,  JINYEONG JOE ,  BONYOUNG KOO ,  DONGSUK SHIN ,  HONGSIK YOON ,  BYEONGCHAN LEE

IPC: H01L29/78 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/02532 ,  H01L21/02636 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/785

Abstract: A semiconductor device includes an active pattern protruding from a substrate, a gate structure crossing over the active pattern, and source/drain regions disposed on the active pattern at opposite sides of the gate structure. Each of the source/drain regions includes a first epitaxial pattern contacting the active pattern and a second epitaxial pattern on the, first epitaxial pattern. The first epitaxial pattern comprises a material having a lattice constant which is the same as that of the substrate, and the second epitaxial pattern comprises a material having a lattice constant greater than that of the first epitaxial pattern.

Abstract translation: 半导体器件包括从衬底突出的有源图案，在有源图案上交叉的栅极结构以及设置在栅极结构的相对侧上的有源图案上的源极/漏极区域。 源极/漏极区域中的每一个包括接触有源图案的第一外延图案和第一外延图案上的第二外延图案。 第一外延图案包括具有与衬底相同的晶格常数的材料，并且第二外延图案包括具有大于第一外延图案的晶格常数的晶格常数的材料。

公开(公告)号：US20180108779A1

公开(公告)日：2018-04-19

申请号：US15844863

申请日：2017-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sujin JUNG ,  JinBum KIM ,  KANG HUN MOON ,  KWAN HEUM LEE ,  BYEONGCHAN LEE ,  Choeun LEE ,  Yang XU

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/7848

Abstract: A semiconductor device is disclosed. The device includes a substrate including an active region defined by a device isolation layer, a fin pattern protruding from the substrate and extending in a first direction, the fin pattern including a gate fin region and a source/drain fin region, a gate pattern disposed on the gate fin region to extend in a second direction crossing the first direction, and a source/drain portion provided on a sidewall of the source/drain fin region. When measured in the second direction, a width of the source/drain fin region is different from a width in the second direction of the gate fin region.

公开(公告)号：US20160351715A1

公开(公告)日：2016-12-01

申请号：US15135566

申请日：2016-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sujin JUNG ,  JinBum KIM ,  KANG HUN MOON ,  KWAN HEUM LEE ,  BYEONGCHAN LEE ,  Choeun LEE ,  Yang XU

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08

CPC classification number: H01L29/7851 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/7848

Abstract: A semiconductor device is disclosed. The device includes a substrate including an active region defined by a device isolation layer, a fin pattern protruding from the substrate and extending in a first direction, the fin pattern including a gate fin region and a source/drain fin region, a gate pattern disposed on the gate fin region to extend in a second direction crossing the first direction, and a source/drain portion provided on a sidewall of the source/drain fin region. When measured in the second direction, a width of the source/drain fin region is different from a width in the second direction of the gate fin region.

Abstract translation: 公开了一种半导体器件。 该器件包括：衬底，其包括由器件隔离层限定的有源区，从衬底突出并沿第一方向延伸的鳍状图案，所述鳍图案包括栅极鳍区和源极/漏极鳍区，栅极图案设置 在所述栅极鳍区域上沿与所述第一方向交叉的第二方向延伸，以及设置在所述源极/漏极鳍片区域的侧壁上的源极/漏极部分。 当在第二方向上测量时，源极/漏极鳍片区域的宽度不同于栅极鳍片区域的第二方向上的宽度。

公开(公告)号：US20150287711A1

公开(公告)日：2015-10-08

申请号：US14562788

申请日：2014-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： SEOKHOON KIM ,  BONYOUNG KOO ,  JinBum KIM ,  CHUL KIM ,  KWAN HEUM LEE ,  BYEONGCHAN LEE ,  Sujin JUNG

IPC: H01L27/02 ,  H01L29/06 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L27/0207 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/7834 ,  H01L29/7848

Abstract: Provided is a semiconductor device which includes a substrate including a first region and a second region different from the first region, a first active pattern provided on the substrate in the first region, a second active pattern provided on the substrate in the second region, a first gate structure crossing over the first active pattern and a second gate structure crossing over the second active pattern, first source/drain regions disposed on the first active pattern at opposite sides of the first gate structure, second source/drain regions disposed on the second active pattern at opposite sides of the second gate structure, and auxiliary spacers disposed in the first region to cover a lower portion of each of the first source/drain regions.

Abstract translation: 提供一种半导体器件，其包括：衬底，其包括第一区域和与第一区域不同的第二区域;设置在第一区域中的衬底上的第一有源图案，设置在第二区域中的衬底上的第二有源图案; 在第一有源图案上交叉的第一栅极结构和与第二有源图案交叉的第二栅极结构，在第一栅极结构的相对侧设置在第一有源图案上的第一源/漏区，设置在第二有源图案上的第二栅极结构的第二栅极结构 在第二栅极结构的相对侧的有源图案以及设置在第一区域中以覆盖每个第一源极/漏极区域的下部的辅助间隔物。