公开(公告)号：US20150287711A1

公开(公告)日：2015-10-08

申请号：US14562788

申请日：2014-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： SEOKHOON KIM ,  BONYOUNG KOO ,  JinBum KIM ,  CHUL KIM ,  KWAN HEUM LEE ,  BYEONGCHAN LEE ,  Sujin JUNG

IPC: H01L27/02 ,  H01L29/06 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L27/0207 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/7834 ,  H01L29/7848

Abstract: Provided is a semiconductor device which includes a substrate including a first region and a second region different from the first region, a first active pattern provided on the substrate in the first region, a second active pattern provided on the substrate in the second region, a first gate structure crossing over the first active pattern and a second gate structure crossing over the second active pattern, first source/drain regions disposed on the first active pattern at opposite sides of the first gate structure, second source/drain regions disposed on the second active pattern at opposite sides of the second gate structure, and auxiliary spacers disposed in the first region to cover a lower portion of each of the first source/drain regions.

Abstract translation: 提供一种半导体器件，其包括：衬底，其包括第一区域和与第一区域不同的第二区域;设置在第一区域中的衬底上的第一有源图案，设置在第二区域中的衬底上的第二有源图案; 在第一有源图案上交叉的第一栅极结构和与第二有源图案交叉的第二栅极结构，在第一栅极结构的相对侧设置在第一有源图案上的第一源/漏区，设置在第二有源图案上的第二栅极结构的第二栅极结构 在第二栅极结构的相对侧的有源图案以及设置在第一区域中以覆盖每个第一源极/漏极区域的下部的辅助间隔物。

公开(公告)号：US20170148901A1

公开(公告)日：2017-05-25

申请号：US15422907

申请日：2017-02-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： KYUNGIN CHOI ,  Sunghyun CHOI ,  Yong-Suk TAK ,  BONYOUNG KOO ,  JAEJONG HAN

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/223

CPC classification number: H01L29/66803 ,  H01L21/2236 ,  H01L21/762 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: A method of manufacturing a semiconductor device includes forming a preliminary fin-type active pattern extending in a first direction, forming a device isolation pattern covering a lower portion of the preliminary fin-type active pattern, forming a gate structure extending in a second direction and crossing over the preliminary fin-type active pattern, forming a fin-type active pattern having a first region and a second region, forming a preliminary impurity-doped pattern on the second region by using a selective epitaxial-growth process, and forming an impurity-doped pattern by injecting impurities using a plasma doping process, wherein the upper surface of the first region is at a first level and the upper surface of the second region is at a second level lower than the first level.

公开(公告)号：US20160315193A1

公开(公告)日：2016-10-27

申请号：US15138914

申请日：2016-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： DONGWOO KIM ,  SEUNGHUN LEE ,  SUNJUNG KIM ,  HYUNJUNG LEE ,  BONYOUNG KOO

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/165 ,  H01L29/08 ,  H01L29/161

CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/7853

Abstract: A semiconductor device can include a substrate and a fin body that protrudes from a surface of the substrate. The fin body can include a lower portion having a first lattice structure and an upper portion, separated from the lower portion by a boundary, the upper portion having a second lattice structure that is different than the first lattice structure. An epitaxially grown epitxial layer can be on the lower and upper portions.

Abstract translation: 半导体器件可以包括从衬底的表面突出的衬底和鳍体。 翅片本体可以包括具有第一格子结构的下部和与下部分开边界的上部，上部具有不同于第一格子结构的第二格子结构。 外延生长的外延层可以在下部和上部。

公开(公告)号：US20170125418A1

公开(公告)日：2017-05-04

申请号：US15407598

申请日：2017-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： JAEYOUNG PARK ,  SUNGHO KANG ,  KICHUL KIM ,  Sunyoung LEE ,  HAN KI LEE ,  BONYOUNG KOO

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L21/306 ,  H01L21/3205 ,  H01L21/762 ,  H01L21/02 ,  H01L29/66 ,  H01L29/45 ,  H01L21/768 ,  H01L29/34 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/0206 ,  H01L21/302 ,  H01L21/306 ,  H01L21/32053 ,  H01L21/76224 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/34 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795

Abstract: A method of manufacturing a semiconductor device includes forming a first plurality of recessed regions in a substrate, the substrate having a protruded active region between the first plurality of recessed regions and the protruded active region having an upper surface and a sidewall, forming a device isolation film in the first plurality of recessed regions, the device isolation film exposing the upper surface and an upper portion of the sidewall of the protruded active region, and performing a first plasma treatment on the exposed surface of the protruded active region, wherein the plasma treatment is performed using a plasma gas containing at least one of an inert gas and a hydrogen gas in a temperature of less than or equal to about 700° C.

公开(公告)号：US20150206956A1

公开(公告)日：2015-07-23

申请号：US14499922

申请日：2014-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： JinBum KIM ,  JUNGHO YOO ,  BYEONGCHAN LEE ,  Choeun LEE ,  HYUN JUNG LEE ,  Seong Hoon JEONG ,  BONYOUNG KOO

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/165 ,  H01L21/8234

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823481 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7848

Abstract: A method of manufacturing a semiconductor device includes forming an active pattern protruding from a semiconductor substrate, forming a dummy gate pattern crossing over the active pattern, forming gate spacers on opposite first and second sidewalls of the dummy gate pattern, removing the dummy gate pattern to form a gate region exposing an upper surface and sidewalls of the active pattern between the gate spacers, recessing the upper surface of the active pattern exposed by the gate region to form a channel recess region, forming a channel pattern in the channel recess region by a selective epitaxial growth (SEG) process, and sequentially forming a gate dielectric layer and a gate electrode covering an upper surface and sidewalls of the channel pattern in the gate region. The channel pattern has a lattice constant different from that of the semiconductor substrate.

Abstract translation: 一种制造半导体器件的方法包括形成从半导体衬底突出的有源图案，形成与有源图案交叉的伪栅极图案，在伪栅极图案的相对的第一和第二侧壁上形成栅极间隔物，将伪栅极图案去除 形成栅极区域，暴露栅极间隔件之间的有源图案的上表面和侧壁，凹陷由栅极区域暴露的有源图案的上表面，以形成通道凹槽区域，在通道凹槽区域中形成通道图案 选择性外延生长（SEG）工艺，以及顺序地形成覆盖栅极区域中的沟道图案的上表面和侧壁的栅极电介质层和栅电极。 沟道图案具有与半导体衬底不同的晶格常数。

公开(公告)号：US20170271479A1

公开(公告)日：2017-09-21

申请号：US15612338

申请日：2017-06-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JINBUM KIM ,  JAEYOUNG PARK ,  DONGHUN LEE ,  JEONGHO YOO ,  JIEON YOON ,  KWAN HEUM LEE ,  CHOEUN LEE ,  BONYOUNG KOO

IPC: H01L29/66 ,  H01L29/12 ,  H01L29/417 ,  H01L29/423 ,  H01L29/40 ,  H01L21/30 ,  H01L29/78 ,  H01L29/08 ,  H01L29/04 ,  H01L29/165

CPC classification number: H01L29/66636 ,  H01L21/3003 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/12 ,  H01L29/165 ,  H01L29/401 ,  H01L29/41766 ,  H01L29/42356 ,  H01L29/66545 ,  H01L29/78

Abstract: A method of fabricating a semiconductor device is provided as follows. A source/drain pattern is formed on a substrate. The source/drain pattern contains silicon atoms and germanium atoms. At least one germanium atom is removed from the germanium atoms of the source/drain pattern.

公开(公告)号：US20150380553A1

公开(公告)日：2015-12-31

申请号：US14673519

申请日：2015-03-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KEUM SEOK PARK ,  JUNGHO YOO ,  JINYEONG JOE ,  BONYOUNG KOO ,  DONGSUK SHIN ,  HONGSIK YOON ,  BYEONGCHAN LEE

IPC: H01L29/78 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/02532 ,  H01L21/02636 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/785

Abstract: A semiconductor device includes an active pattern protruding from a substrate, a gate structure crossing over the active pattern, and source/drain regions disposed on the active pattern at opposite sides of the gate structure. Each of the source/drain regions includes a first epitaxial pattern contacting the active pattern and a second epitaxial pattern on the, first epitaxial pattern. The first epitaxial pattern comprises a material having a lattice constant which is the same as that of the substrate, and the second epitaxial pattern comprises a material having a lattice constant greater than that of the first epitaxial pattern.

Abstract translation: 半导体器件包括从衬底突出的有源图案，在有源图案上交叉的栅极结构以及设置在栅极结构的相对侧上的有源图案上的源极/漏极区域。 源极/漏极区域中的每一个包括接触有源图案的第一外延图案和第一外延图案上的第二外延图案。 第一外延图案包括具有与衬底相同的晶格常数的材料，并且第二外延图案包括具有大于第一外延图案的晶格常数的晶格常数的材料。