公开(公告)号：US20180286861A1

公开(公告)日：2018-10-04

申请号：US15793442

申请日：2017-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： KYUNGIN CHOI ,  Taehyeon KIM ,  HONGSHIK SHIN ,  TAEGON KIM ,  JAEYOUNG PARK ,  YUICHIRO SASAKI

IPC: H01L27/092 ,  H01L21/768 ,  H01L21/225

CPC classification number: H01L27/0922 ,  H01L21/2253 ,  H01L21/76841 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/161 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/785

Abstract: A method of fabricating a semiconductor device includes pattering an upper portion of a substrate to form a first active pattern, the substrate including a semiconductor element having a first lattice constant, performing a selective epitaxial growth process on an upper portion of the first active pattern to form a first source/drain region, doping the first source/drain region with gallium, performing an annealing process on the first source/drain region doped with gallium, and forming a first contact pattern coupled to the first source/drain region. The first source/drain region includes a semiconductor element having a second lattice constant larger than the first lattice constant.

公开(公告)号：US20170125418A1

公开(公告)日：2017-05-04

申请号：US15407598

申请日：2017-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： JAEYOUNG PARK ,  SUNGHO KANG ,  KICHUL KIM ,  Sunyoung LEE ,  HAN KI LEE ,  BONYOUNG KOO

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L21/306 ,  H01L21/3205 ,  H01L21/762 ,  H01L21/02 ,  H01L29/66 ,  H01L29/45 ,  H01L21/768 ,  H01L29/34 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/0206 ,  H01L21/302 ,  H01L21/306 ,  H01L21/32053 ,  H01L21/76224 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/34 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795

Abstract: A method of manufacturing a semiconductor device includes forming a first plurality of recessed regions in a substrate, the substrate having a protruded active region between the first plurality of recessed regions and the protruded active region having an upper surface and a sidewall, forming a device isolation film in the first plurality of recessed regions, the device isolation film exposing the upper surface and an upper portion of the sidewall of the protruded active region, and performing a first plasma treatment on the exposed surface of the protruded active region, wherein the plasma treatment is performed using a plasma gas containing at least one of an inert gas and a hydrogen gas in a temperature of less than or equal to about 700° C.

公开(公告)号：US20210013204A1

公开(公告)日：2021-01-14

申请号：US17015307

申请日：2020-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： KYUNGIN CHOI ,  Taehyeon KIM ,  HONGSHIK SHIN ,  TAEGON KIM ,  JAEYOUNG PARK ,  YUICHIRO SASAKI

IPC: H01L27/092 ,  H01L21/225 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417

Abstract: A method of fabricating a semiconductor device includes pattering an upper portion of a substrate to form a first active pattern, the substrate including a semiconductor element having a first lattice constant, performing a selective epitaxial growth process on an upper portion of the first active pattern to form a first source/drain region, doping the first source/drain region with gallium, performing an annealing process on the first source/drain region doped with gallium, and forming a first contact pattern coupled to the first source/drain region. The first source/drain region includes a semiconductor element having a second lattice constant larger than the first lattice constant.

公开(公告)号：US20190287969A1

公开(公告)日：2019-09-19

申请号：US16419318

申请日：2019-05-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： KYUNGIN CHOI ,  Taehyeon KIM ,  HONGSHIK SHIN ,  TAEGON KIM ,  JAEYOUNG PARK ,  YUICHIRO SASAKI

IPC: H01L27/092 ,  H01L21/225 ,  H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

Abstract: A method of fabricating a semiconductor device includes pattering an upper portion of a substrate to form a first active pattern, the substrate including a semiconductor element having a first lattice constant, performing a selective epitaxial growth process on an upper portion of the first active pattern to form a first source/drain region, doping the first source/drain region with gallium, performing an annealing process on the first source/drain region doped with gallium, and forming a first contact pattern coupled to the first source/drain region. The first source/drain region includes a semiconductor element having a second lattice constant larger than the first lattice constant.

公开(公告)号：US20170271479A1

公开(公告)日：2017-09-21

申请号：US15612338

申请日：2017-06-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JINBUM KIM ,  JAEYOUNG PARK ,  DONGHUN LEE ,  JEONGHO YOO ,  JIEON YOON ,  KWAN HEUM LEE ,  CHOEUN LEE ,  BONYOUNG KOO

IPC: H01L29/66 ,  H01L29/12 ,  H01L29/417 ,  H01L29/423 ,  H01L29/40 ,  H01L21/30 ,  H01L29/78 ,  H01L29/08 ,  H01L29/04 ,  H01L29/165

CPC classification number: H01L29/66636 ,  H01L21/3003 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/12 ,  H01L29/165 ,  H01L29/401 ,  H01L29/41766 ,  H01L29/42356 ,  H01L29/66545 ,  H01L29/78

Abstract: A method of fabricating a semiconductor device is provided as follows. A source/drain pattern is formed on a substrate. The source/drain pattern contains silicon atoms and germanium atoms. At least one germanium atom is removed from the germanium atoms of the source/drain pattern.