公开(公告)号：US20230326970A1

公开(公告)日：2023-10-12

申请号：US18050684

申请日：2022-10-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Namkyu CHO ,  Seokhoon KIM ,  Jeongho YOO ,  Choeun LEE ,  Pankwi PARK ,  Dongsuk SHIN

IPC: H01L29/08 ,  H01L29/786 ,  H01L27/092 ,  H01L29/66 ,  H01L29/775 ,  H01L29/40 ,  H01L29/423 ,  H01L29/417 ,  H01L21/8238

CPC classification number: H01L29/0847 ,  H01L29/78696 ,  H01L27/092 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/41783 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/0673

Abstract: A semiconductor device includes a substrate including a first active pattern, a first channel pattern on the first active pattern, the first channel pattern including first, second, and third semiconductor patterns spaced apart from one another and vertically stacked, a first source/drain pattern connected to the first to third semiconductor patterns, and a gate electrode on the first to third semiconductor patterns. The first source/drain pattern includes a first protrusion protruding toward the first semiconductor pattern, a second protrusion protruding toward the second semiconductor pattern, and a third protrusion protruding toward the third semiconductor pattern. A width of the second protrusion is greater than a width of the first protrusion. A width of the third protrusion is greater than the width of the second protrusion.

公开(公告)号：US20250048699A1

公开(公告)日：2025-02-06

申请号：US18607960

申请日：2024-03-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Hwan KIM ,  Unki KIM ,  Chanyoung KIM ,  Jeongho YOO ,  Ingyu JANG ,  Sujin JUNG

IPC: H01L29/10 ,  H01L29/08 ,  H01L29/423

Abstract: A semiconductor device includes a substrate including an active pattern, a channel pattern and a source/drain pattern on the active pattern wherein the channel pattern includes semiconductor patterns vertically stacked and spaced apart from each other, the plurality of semiconductor patterns including a first semiconductor pattern and a neighboring second semiconductor pattern, and a gate electrode on the semiconductor patterns. The gate electrode includes an inner electrode between the first and second semiconductor patterns. The source/drain pattern includes a buffer layer and a main layer on the buffer layer. An indent region is defined in a vertical cross section of the device by the main layer, the first and second semiconductor patterns, and the inner electrode. The buffer layer is in the indent region. The buffer layer does not extend onto sidewalls of the first and second semiconductor patterns.

公开(公告)号：US20190139811A1

公开(公告)日：2019-05-09

申请号：US15869718

申请日：2018-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunguk Jang ,  Seokhoon KIM ,  Seung Hun LEE ,  Yang XU ,  Jeongho YOO ,  Jongryeol YOO ,  Youngdae CHO

IPC: H01L21/762 ,  H01L29/66 ,  H01L29/423 ,  H01L29/165 ,  H01L21/02 ,  H01L21/225

Abstract: Semiconductor devices and methods of forming the same are provided. The methods may implanting dopants into a substrate to form a preliminary impurity region and heating the substrate to convert the preliminary impurity region into an impurity region. Heating the substrate may be performed at an ambient temperature of from about 800° C. to about 950° C. for from about 20 min to about 50 min. The method may also include forming first and second trenches in the impurity region to define an active tin and forming a first isolation layer and a second isolation layer in the first and second trenches, respectively. The first and second isolation layers may expose opposing sides of the active fin. The method may further include forming a gate insulation layer extending on the opposing sides and an upper surface of the active fin and forming a gate electrode traversing the active fin

公开(公告)号：US20210143049A1

公开(公告)日：2021-05-13

申请号：US17137485

申请日：2020-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunguk Jang ,  Seokhoon KIM ,  Seung Hun LEE ,  Yang XU ,  Jeongho YOO ,  Jongryeol YOO ,  Youngdae CHO

IPC: H01L21/762 ,  H01L21/225 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66 ,  H01L29/165 ,  H01L29/78

Abstract: Semiconductor devices and methods of forming the same are provided. The methods may implanting dopants into a substrate to form a preliminary impurity region and heating the substrate to convert the preliminary impurity region into an impurity region. Heating the substrate may be performed at an ambient temperature of from about 800° C. to about 950° C. for from about 20 min to about 50 min. The method may also include forming first and second trenches in the impurity region to define an active fin and forming a first isolation layer and a second isolation layer in the first and second trenches, respectively. The first and second isolation layers may expose opposing sides of the active fin. The method may further include forming a gate insulation layer extending on the opposing sides and an upper surface of the active fin and forming a gate electrode traversing the active fin

公开(公告)号：US20210408241A1

公开(公告)日：2021-12-30

申请号：US17471244

申请日：2021-09-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seojin JEONG ,  Jinyeong JOE ,  Seokhoon KIM ,  Jeongho YOO ,  Seung Hun LEE ,  Sihyung LEE

IPC: H01L29/16 ,  H01L29/10 ,  H01L29/04 ,  H01L29/167 ,  H01L29/36 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/762 ,  H01L29/66 ,  H01L29/08

Abstract: A semiconductor device includes a substrate, a device isolation layer on the substrate, the device isolation layer defining a first active pattern, a pair of first source/drain patterns on the first active pattern, the pair of first source/drain patterns being spaced apart from each other in a first direction, and each of the pair of first source/drain patterns having a maximum first width in the first direction, a first channel pattern between the pair of first source/drain patterns, a gate electrode on the first channel pattern and extends in a second direction intersecting the first direction, and a first amorphous region in the first active pattern, the first amorphous region being below at least one of the pair of first source/drain patterns, and having a maximum second width in the first direction that is less than the maximum first width.

公开(公告)号：US20200075764A1

公开(公告)日：2020-03-05

申请号：US16412796

申请日：2019-05-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunguk JANG ,  Sujin JUNG ,  Jinyeong JOE ,  Jeongho YOO ,  Seung Hun LEE ,  Jongryeol YOO

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L27/088

Abstract: A semiconductor device includes a first active fin protruding from a substrate, a first gate pattern covering a side surface and a top surface of the first active fin, and first source/drain patterns at opposite sides of the first gate pattern, each of the first source/drain patterns including a first lower side and a second lower side spaced apart from each other, a first upper side extended from the first lower side, a second upper side extended from the second lower side. The first lower side may be inclined at a first angle relative to a top surface of the substrate, the second upper side may be inclined at a second angle relative to the top surface of the substrate, and the first angle may be greater than the second angle.