公开(公告)号：US20250048699A1

公开(公告)日：2025-02-06

申请号：US18607960

申请日：2024-03-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Hwan KIM ,  Unki KIM ,  Chanyoung KIM ,  Jeongho YOO ,  Ingyu JANG ,  Sujin JUNG

IPC: H01L29/10 ,  H01L29/08 ,  H01L29/423

Abstract: A semiconductor device includes a substrate including an active pattern, a channel pattern and a source/drain pattern on the active pattern wherein the channel pattern includes semiconductor patterns vertically stacked and spaced apart from each other, the plurality of semiconductor patterns including a first semiconductor pattern and a neighboring second semiconductor pattern, and a gate electrode on the semiconductor patterns. The gate electrode includes an inner electrode between the first and second semiconductor patterns. The source/drain pattern includes a buffer layer and a main layer on the buffer layer. An indent region is defined in a vertical cross section of the device by the main layer, the first and second semiconductor patterns, and the inner electrode. The buffer layer is in the indent region. The buffer layer does not extend onto sidewalls of the first and second semiconductor patterns.

公开(公告)号：US20240203989A1

公开(公告)日：2024-06-20

申请号：US18227064

申请日：2023-07-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinbum KIM ,  Gyeom KIM ,  Youngkwang KIM ,  Chanyoung KIM ,  Jangwoo PARK ,  Sangmoon LEE ,  Sujin JUNG

IPC: H01L27/092 ,  H01L29/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/161 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L27/092 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/775

Abstract: A semiconductor device includes a substrate including a p-type metal-oxide-semiconductor (MOS) field-effect transistor (FET) (PMOSFET) region and an n-type MOSFET (NMOSFET) region, a first active pattern on the PMOSFET region, a second active pattern on the NMOSFET region, a first channel pattern and a first source/drain pattern on the first active pattern, the first channel pattern connected to the first source/drain pattern, a second channel pattern and a second source/drain pattern provided on the second active pattern, the second channel pattern connected to the second source/drain pattern, and a gate electrode on the first channel pattern and the second channel pattern.

公开(公告)号：US20240196599A1

公开(公告)日：2024-06-13

申请号：US18512135

申请日：2023-11-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaekang KOH ,  Byeongguk KO ,  Chanyoung KIM ,  Sangkoo NAM ,  Yongsoon CHOI

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/315

Abstract: A semiconductor device includes: an active pattern disposed on a substrate; a gate structure disposed on the active pattern; a bit line structure disposed on the active pattern, and including a first conductive pattern, a second conductive pattern and an insulation structure stacked on each other, a lower spacer structure disposed on a sidewall of the bit line structure; an upper spacer structure disposed on the lower spacer structure, wherein the upper spacer structure is disposed on an upper portion of the sidewall of the bit line structure; a contact plug structure disposed on the active pattern, wherein the contact plug structure is spaced apart from the bit line structure; and a capacitor disposed on the contact plug structure, wherein the lower spacer structure includes: a first spacer partially covering a sidewall of the first conductive pattern, and including air; and a second spacer disposed on the first spacer.