公开(公告)号：US20240243188A1

公开(公告)日：2024-07-18

申请号：US18513759

申请日：2023-11-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyohoon BYEON ,  Seokhoon KIM ,  Unki KIM ,  Pankwi PARK ,  Sungkeun LIM ,  Yuyeong JO

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/66545 ,  H01L21/823425 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: An integrated circuit device includes: a rear wiring structure; an insulating substrate including fin structures disposed on the rear wiring structure and extending in a first horizontal direction; a device isolation layer disposed between the fin structures; a lower insulating layer covering the fin structures; gate structures extending in a second horizontal direction crossing the first horizontal direction; a plurality of nanosheet stacks disposed on the lower insulating layer; a first source/drain region disposed on the insulating substrate and including a body portion and a vertical extension portion, wherein the body portion is disposed between the plurality of nanosheet stacks, and the vertical extension portion passes through the lower insulating layer and through some of the fin structures; a semiconductor epitaxial structure at least partially surrounding the vertical extension portion of the first source/drain region; and a lower contact connecting the semiconductor epitaxial structure with the rear wiring structure.

公开(公告)号：US20250048699A1

公开(公告)日：2025-02-06

申请号：US18607960

申请日：2024-03-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Hwan KIM ,  Unki KIM ,  Chanyoung KIM ,  Jeongho YOO ,  Ingyu JANG ,  Sujin JUNG

IPC: H01L29/10 ,  H01L29/08 ,  H01L29/423

Abstract: A semiconductor device includes a substrate including an active pattern, a channel pattern and a source/drain pattern on the active pattern wherein the channel pattern includes semiconductor patterns vertically stacked and spaced apart from each other, the plurality of semiconductor patterns including a first semiconductor pattern and a neighboring second semiconductor pattern, and a gate electrode on the semiconductor patterns. The gate electrode includes an inner electrode between the first and second semiconductor patterns. The source/drain pattern includes a buffer layer and a main layer on the buffer layer. An indent region is defined in a vertical cross section of the device by the main layer, the first and second semiconductor patterns, and the inner electrode. The buffer layer is in the indent region. The buffer layer does not extend onto sidewalls of the first and second semiconductor patterns.

公开(公告)号：US20250120121A1

公开(公告)日：2025-04-10

申请号：US18733327

申请日：2024-06-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Unki KIM ,  Kihwan Kim ,  Chanyoung Kim ,  Jeongho Yoo ,  Ingyu Jang ,  Sujin Jung

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/16 ,  H01L29/167 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A semiconductor memory device is provided. The semiconductor memory device includes: a substrate; an active region extending in a first direction on the substrate; a plurality of channel layers stacked on the active region and spaced apart from each other in a vertical direction perpendicular to the first direction; a gate structure extending on the active region in a second direction perpendicular to the first direction and the vertical direction, and surrounding the plurality of channel layers; a source/drain region provided on at least one side of the gate structure on the active region and electrically connected to the plurality of channel layers; and a plurality of anti-diffusion layers stacked and spaced apart from each other in the vertical direction and extending in the second direction.

公开(公告)号：US20230081646A1

公开(公告)日：2023-03-16

申请号：US17902111

申请日：2022-09-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhyun KIM ,  Unki KIM ,  Alum JUNG ,  Kyung-Eun BYUN

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/161 ,  H01L29/423 ,  H01L29/775 ,  H01L21/02 ,  H01L21/306 ,  H01L29/66

Abstract: A multi bridge channel field effect transistor includes a substrate, a first source/drain pattern on the substrate, a second source/drain pattern apart from the first source/drain pattern in a first direction on the substrate, a first channel layer and a second channel layer between the first source/drain pattern and the second source/drain pattern, a first graphene barrier between the first channel layer and the first source/drain pattern, a gate insulating layer surrounding the first channel layer, and a gate electrode surrounding the first channel layer with the gate insulating layer therebetween.