公开(公告)号：US20250120121A1

公开(公告)日：2025-04-10

申请号：US18733327

申请日：2024-06-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Unki KIM ,  Kihwan Kim ,  Chanyoung Kim ,  Jeongho Yoo ,  Ingyu Jang ,  Sujin Jung

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/16 ,  H01L29/167 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A semiconductor memory device is provided. The semiconductor memory device includes: a substrate; an active region extending in a first direction on the substrate; a plurality of channel layers stacked on the active region and spaced apart from each other in a vertical direction perpendicular to the first direction; a gate structure extending on the active region in a second direction perpendicular to the first direction and the vertical direction, and surrounding the plurality of channel layers; a source/drain region provided on at least one side of the gate structure on the active region and electrically connected to the plurality of channel layers; and a plurality of anti-diffusion layers stacked and spaced apart from each other in the vertical direction and extending in the second direction.

公开(公告)号：US20250048696A1

公开(公告)日：2025-02-06

申请号：US18609885

申请日：2024-03-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KI HWAN KIM ,  Unki Kim ,  Chanyoung Kim ,  Jeongho Yoo ,  Ingyu Jang ,  Sujin Jung

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A semiconductor device includes a substrate including an active pattern, a channel pattern on the active pattern, the channel pattern including a first semiconductor pattern, a second semiconductor pattern, and a third semiconductor pattern sequentially stacked and vertically spaced apart, a source/drain pattern on the active pattern, and a gate electrode on the first semiconductor pattern, the second semiconductor pattern, and the third semiconductor pattern, where the source/drain pattern includes a buffer layer and a main layer on the buffer layer, the main layer includes silicon that is doped with an impurity, an impurity concentration of the main layer is a first atomic fraction at a first level corresponding to the first semiconductor pattern, and the impurity concentration of the main layer is a second atomic fraction at a second level corresponding to the second semiconductor pattern.