公开(公告)号：US20230268395A1

公开(公告)日：2023-08-24

申请号：US18062713

申请日：2022-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinbum KIM ,  Sujin JUNG ,  Gyeom KIM ,  Dahye KIM ,  Ingyu JANG ,  Kyungbin CHUN

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L21/764 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L21/764 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/66439

Abstract: A semiconductor device includes; a gate structure intersecting an active region, and a plurality of channel layers, extending on the substrate in a second direction, and surrounding the plurality of channel layers; a source/drain region contacting the plurality of channel layers on at least one side of the gate structure and including a first semiconductor material with first impurities having a first conductivity type; and a lower structure in contact with the active region and below the source/drain region. The lower structure includes a first layer disposed on the active region and including an insulating material; a second layer disposed on the first layer and including a second semiconductor material; with an air gap defined by the first layer and the second layer, wherein the second semiconductor material of the second layer has no conductivity type or has a second conductivity type different from the first conductivity type.

公开(公告)号：US20250048699A1

公开(公告)日：2025-02-06

申请号：US18607960

申请日：2024-03-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Hwan KIM ,  Unki KIM ,  Chanyoung KIM ,  Jeongho YOO ,  Ingyu JANG ,  Sujin JUNG

IPC: H01L29/10 ,  H01L29/08 ,  H01L29/423

Abstract: A semiconductor device includes a substrate including an active pattern, a channel pattern and a source/drain pattern on the active pattern wherein the channel pattern includes semiconductor patterns vertically stacked and spaced apart from each other, the plurality of semiconductor patterns including a first semiconductor pattern and a neighboring second semiconductor pattern, and a gate electrode on the semiconductor patterns. The gate electrode includes an inner electrode between the first and second semiconductor patterns. The source/drain pattern includes a buffer layer and a main layer on the buffer layer. An indent region is defined in a vertical cross section of the device by the main layer, the first and second semiconductor patterns, and the inner electrode. The buffer layer is in the indent region. The buffer layer does not extend onto sidewalls of the first and second semiconductor patterns.

公开(公告)号：US20250133793A1

公开(公告)日：2025-04-24

申请号：US18663416

申请日：2024-05-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongryeol YOO ,  Jaejun KIM ,  Ingyu JANG ,  Gwangjun KIM ,  Sunghwan KIM ,  Jiwon JEONG ,  Jeongsang PYO

IPC: H01L29/36 ,  H01L29/167

Abstract: A semiconductor device includes a substrate; an active pattern extending on the substrate in a first direction; a plurality of channel layers on the active pattern and spaced apart from each other in a vertical direction; a gate structure crossing the active pattern, the gate structure surrounding the plurality of channel layers and extending in a second direction orthogonal to the first direction; and source/drain patterns on a region of the active pattern on both sides of the gate structure, and having a semiconductor liner layer connected to each of side surfaces of the plurality of channel layers, and a semiconductor filling layer on the semiconductor liner layer. The semiconductor liner layer includes silicon-germanium (SiGe) doped with a first conductivity-type impurity. The semiconductor filling layer includes an epitaxial layer having a germanium (Ge) concentration higher than that of the semiconductor liner layer, and the epitaxial layer is doped with Ga.

公开(公告)号：US20230100189A1

公开(公告)日：2023-03-30

申请号：US17730928

申请日：2022-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dahye KIM ,  Sujin JUNG ,  Ingyu JANG ,  Jinbum KIM

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/417

Abstract: A semiconductor device includes a fin-type active region that protrudes from a substrate and extends in a first direction, a plurality of channel layers on the fin-type active region that are spaced apart from each other in a second direction that is perpendicular to an upper surface of the substrate, a gate structure that intersects the fin-type active region, extends in the second direction, and surrounds each of the plurality of channel layers in a third direction, fence spacers on side surfaces of the fin-type active region in the second direction on sides of the gate structure and extending in the second direction, and a source/drain region between the fence spacers on the fin-type active region at sides of the gate structure, connected to each of the plurality of channel layers, and having voids in side surfaces adjacent the fence spacers.