公开(公告)号：US20190139811A1

公开(公告)日：2019-05-09

申请号：US15869718

申请日：2018-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunguk Jang ,  Seokhoon KIM ,  Seung Hun LEE ,  Yang XU ,  Jeongho YOO ,  Jongryeol YOO ,  Youngdae CHO

IPC: H01L21/762 ,  H01L29/66 ,  H01L29/423 ,  H01L29/165 ,  H01L21/02 ,  H01L21/225

Abstract: Semiconductor devices and methods of forming the same are provided. The methods may implanting dopants into a substrate to form a preliminary impurity region and heating the substrate to convert the preliminary impurity region into an impurity region. Heating the substrate may be performed at an ambient temperature of from about 800° C. to about 950° C. for from about 20 min to about 50 min. The method may also include forming first and second trenches in the impurity region to define an active tin and forming a first isolation layer and a second isolation layer in the first and second trenches, respectively. The first and second isolation layers may expose opposing sides of the active fin. The method may further include forming a gate insulation layer extending on the opposing sides and an upper surface of the active fin and forming a gate electrode traversing the active fin

公开(公告)号：US20220199618A1

公开(公告)日：2022-06-23

申请号：US17383749

申请日：2021-07-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sujin JUNG ,  Kihwan KIM ,  Sunguk JANG ,  Youngdae CHO

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78

Abstract: An integrated circuit (IC) device includes a fin-type active region extending longitudinally in a first lateral direction on a substrate. A nanosheet is apart from a fin top surface of the fin-type active region in a vertical direction. An inner insulating spacer is between the substrate and the nanosheet. A gate line includes a main gate portion and a sub-gate portion. The main gate portion extends longitudinally in a second lateral direction on the nanosheet. The sub-gate portion is integrally connected to the main gate portion and between the substrate and the nanosheet. A source/drain region is in contact with the inner insulating spacer and the nanosheet. The source/drain region includes a single crystalline semiconductor body and at least one lower stacking fault surface linearly extending from the inner insulating spacer through the single crystalline semiconductor body.

公开(公告)号：US20220005958A1

公开(公告)日：2022-01-06

申请号：US17480457

申请日：2021-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunguk JANG ,  Kihwan KIM ,  Sujin JUNG ,  Youngdae CHO

IPC: H01L29/786 ,  H01L29/08 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66

Abstract: A semiconductor device includes an active region on a substrate extending in a first direction, the active region having an upper surface and sidewalls, a plurality of channel layers above the active region to be vertically spaced apart from each other, a gate electrode extending in a second direction to intersect the active region and partially surrounding the plurality of channel layers, and a source/drain region on the active region on at least one side of the gate electrode and in contact with the plurality of channel layers, and extending from the sidewalls of the active region having a major width in the second direction in a first region adjacent to a lowermost channel layer adjacent to the active region among the plurality of channel layer.

公开(公告)号：US20230307498A1

公开(公告)日：2023-09-28

申请号：US18205671

申请日：2023-06-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sujin JUNG ,  Kihwan KIM ,  Sunguk JANG ,  Youngdae CHO

IPC: H01L29/10 ,  H01L29/16 ,  H01L29/06 ,  H01L29/78 ,  H01L29/08 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/1037 ,  H01L29/1608 ,  H01L29/0653 ,  H01L29/785 ,  H01L29/0847 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78696

Abstract: A semiconductor device including: an active pattern on a substrate, the active pattern including a recess, the recess having a “V” shape; a growth prevention pattern on the recess; gate structures on portions of the active pattern at opposite sides of the recess; channels spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, each of the channels extending through one of the gate structures; and a source/drain layer on the growth prevention pattern, the source/drain layer contacting the channels.

公开(公告)号：US20220216348A1

公开(公告)日：2022-07-07

申请号：US17489181

申请日：2021-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kihwan KIM ,  Sunguk JANG ,  Sujin JUNG ,  Youngdae CHO

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/167 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66

Abstract: A semiconductor device includes an active region extending in a first direction on a substrate, a plurality of channel layers vertically spaced apart from each other on the active region and including a semiconductor material, a gate structure extending in a second direction on the substrate, and a source/drain region disposed on the active region on at least one side of the gate structure. The gate structure intersects the active region and the plurality of channel layers, and surrounds the plurality of channel layers. The source/drain region contacts the plurality of channel layers and includes first impurities. In at least a portion of the plurality of channel layers, a lower region adjacent to the active region includes the first impurities and second impurities at a first concentration, and an upper region includes the first impurities and the second impurities at a second concentration lower than the first concentration.

公开(公告)号：US20250040185A1

公开(公告)日：2025-01-30

申请号：US18596247

申请日：2024-03-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyojin KIM ,  Youngdae CHO ,  Sungkeun LIM

IPC: H01L29/417 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device may include a substrate layer; a source/drain epitaxial layer between first channel layers and second channel layers; a backside contact structure electrically connected to the source/drain epitaxial layer, wherein the backside contact structure is between the source/drain epitaxial layer and a lower surface of the substrate layer, first width of the source/drain epitaxial layer at an upper surface of the substrate layer is greater than a second width at an interface between the source/drain epitaxial layer and the backside contact structure, a first portion of the backside contact structure is closer than a closest end of the source/drain epitaxial layer to the lower surface of the substrate layer, the first portion of the backside contact structure has a third width, and the third width is greater than the second width.

公开(公告)号：US20220115514A1

公开(公告)日：2022-04-14

申请号：US17559347

申请日：2021-12-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sujin JUNG ,  Kihwan KIM ,  Sunguk JANG ,  Youngdae CHO

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/08

Abstract: A semiconductor device including: an active pattern on a substrate, the active pattern including a recess, the recess having a “V” shape; a growth prevention pattern on the recess; gate structures on portions of the active pattern at opposite sides of the recess; channels spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, each of the channels extending through one of the gate structures; and a source/drain layer on the growth prevention pattern, the source/drain layer contacting the channels.

公开(公告)号：US20210143049A1

公开(公告)日：2021-05-13

申请号：US17137485

申请日：2020-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunguk Jang ,  Seokhoon KIM ,  Seung Hun LEE ,  Yang XU ,  Jeongho YOO ,  Jongryeol YOO ,  Youngdae CHO

IPC: H01L21/762 ,  H01L21/225 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66 ,  H01L29/165 ,  H01L29/78

Abstract: Semiconductor devices and methods of forming the same are provided. The methods may implanting dopants into a substrate to form a preliminary impurity region and heating the substrate to convert the preliminary impurity region into an impurity region. Heating the substrate may be performed at an ambient temperature of from about 800° C. to about 950° C. for from about 20 min to about 50 min. The method may also include forming first and second trenches in the impurity region to define an active fin and forming a first isolation layer and a second isolation layer in the first and second trenches, respectively. The first and second isolation layers may expose opposing sides of the active fin. The method may further include forming a gate insulation layer extending on the opposing sides and an upper surface of the active fin and forming a gate electrode traversing the active fin