公开(公告)号：US20240196602A1

公开(公告)日：2024-06-13

申请号：US18490212

申请日：2023-10-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhee CHOI ,  Daejin NAM ,  Sunguk JANG

IPC: H10B12/00 ,  H01L29/423

CPC classification number: H10B12/485 ,  H01L29/42356 ,  H10B12/482 ,  H10B12/488

Abstract: An integrated circuit device includes a substrate having an active region, a word line extending in the substrate in a first horizontal direction, a bit line extending on the word line in a second horizontal direction, a bit line contact electrically connecting the bit line to the active region, a doping contact connecting the bit line contact to the active region, a cell pad having a horizontal width greater than that of the active region, a buried contact that digs into one side wall of the cell pad, and a conductive landing pad facing the bit line in the first horizontal direction. The doping contact includes a first doping contact and a second doping contact, and a thickness of the first doping contact in the vertical direction is less than that of the second doping contact in the vertical direction.

公开(公告)号：US20220149210A1

公开(公告)日：2022-05-12

申请号：US17584545

申请日：2022-01-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Mo KANG ,  Moon Seung YANG ,  Jongryeol YOO ,  Sihyung LEE ,  Sunguk JANG ,  Eunhye CHOI

IPC: H01L29/786 ,  H01L29/08 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/311

Abstract: A semiconductor device includes a channel pattern including first and second semiconductor patterns stacked on a substrate, a gate electrode covering top and lateral surfaces of the channel pattern and extending in a first direction, and including a first gate segment between the first semiconductor pattern and the second semiconductor pattern, a gate spacer covering a lateral surface of the gate electrode and including an opening exposing the channel pattern, and a first source/drain pattern on a side of the gate spacer and in contact with the channel pattern through the opening, the first source/drain pattern including a sidewall center thickness at a height of the first gate segment and at a center of the opening, and a sidewall edge thickness at the height of the first gate segment and at an edge of the opening, the sidewall edge thickness being about 0.7 to 1 times the sidewall center thickness.

公开(公告)号：US20250142811A1

公开(公告)日：2025-05-01

申请号：US18890123

申请日：2024-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyojin PARK ,  Jinbum KIM ,  Sung-Hwan JANG ,  Dae-Jin NAM ,  Sunguk JANG

IPC: H10B12/00

Abstract: A semiconductor memory device may include bit lines spaced apart from each other in a first direction on a substrate and extending in a second direction, a first active pattern and a second active pattern on the bit lines and are spaced apart from each other in the second direction, and first and second word lines between the first active and second active patterns. The first and second word lines respectively may be adjacent to the first and second active patterns. The first active pattern and/or the second active pattern may include a body portion extending in a third direction and a protruding portion protruding from an upper end of the body portion in the third direction. The protruding portion may have a width in the second direction that is greater than that of the body portion. The third direction may differ from the first and second directions.

公开(公告)号：US20250048621A1

公开(公告)日：2025-02-06

申请号：US18641488

申请日：2024-04-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunghwan JANG ,  Jinbum KIM ,  Hyojin PARK ,  Sunguk JANG

IPC: H10B12/00 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor memory device includes: a plurality of word lines extending in a first direction; a plurality of channel layers alternately arranged with the word lines, wherein the channel layers extend in a second direction; and a plurality of bit lines located on the word lines and the channel layers, and extending in a third direction. The bit lines are electrically connected to the channel layers. The plurality of word lines include: a plurality of selected word lines to which a positive voltage is applied; and a plurality of non-selected word lines to which a negative voltage is applied. The plurality of channel layers include: a selected channel layer that is turned on; and a non-selected channel layer that is turned off.

公开(公告)号：US20220199618A1

公开(公告)日：2022-06-23

申请号：US17383749

申请日：2021-07-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sujin JUNG ,  Kihwan KIM ,  Sunguk JANG ,  Youngdae CHO

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78

Abstract: An integrated circuit (IC) device includes a fin-type active region extending longitudinally in a first lateral direction on a substrate. A nanosheet is apart from a fin top surface of the fin-type active region in a vertical direction. An inner insulating spacer is between the substrate and the nanosheet. A gate line includes a main gate portion and a sub-gate portion. The main gate portion extends longitudinally in a second lateral direction on the nanosheet. The sub-gate portion is integrally connected to the main gate portion and between the substrate and the nanosheet. A source/drain region is in contact with the inner insulating spacer and the nanosheet. The source/drain region includes a single crystalline semiconductor body and at least one lower stacking fault surface linearly extending from the inner insulating spacer through the single crystalline semiconductor body.

公开(公告)号：US20250040245A1

公开(公告)日：2025-01-30

申请号：US18602827

申请日：2024-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Suk YANG ,  Sung-Hwan JANG ,  Jinbum KIM ,  Sunguk JANG

IPC: H01L27/118

Abstract: A semiconductor device includes a substrate, a first device region on the substrate, a second device region on the substrate and spaced apart from the first device region in a first direction, a first dummy region between the first device region and the second device region, and an insulating pattern in the first device region, the second device region and the first dummy region, where the first dummy region includes a seed pattern on the insulating pattern, and a seed mask pattern at least partially covering a top surface of the seed pattern and extending from the top surface of the seed pattern along a first sidewall of the seed pattern, where the insulating pattern in the first dummy region is on the substrate, and where the seed pattern includes a transition metal dichalcogenide.

公开(公告)号：US20250016993A1

公开(公告)日：2025-01-09

申请号：US18428207

申请日：2024-01-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Hwan JANG ,  Guifu YANG ,  Jinbum KIM ,  Sunguk JANG

IPC: H10B12/00

Abstract: A semiconductor device includes a substrate including a recess region; a bit line contact in the recess region; a bit line on the bit line contact, the bit line extending in a first direction; a first insulating pattern covering side surfaces of the bit line contact and an inner surface of the recess region; and a second insulating pattern on the first insulating pattern, wherein an oxygen density of the first insulating pattern is higher than an oxygen density of the second insulating pattern.

公开(公告)号：US20220115514A1

公开(公告)日：2022-04-14

申请号：US17559347

申请日：2021-12-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sujin JUNG ,  Kihwan KIM ,  Sunguk JANG ,  Youngdae CHO

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/08

Abstract: A semiconductor device including: an active pattern on a substrate, the active pattern including a recess, the recess having a “V” shape; a growth prevention pattern on the recess; gate structures on portions of the active pattern at opposite sides of the recess; channels spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, each of the channels extending through one of the gate structures; and a source/drain layer on the growth prevention pattern, the source/drain layer contacting the channels.

公开(公告)号：US20200381564A1

公开(公告)日：2020-12-03

申请号：US16774653

申请日：2020-01-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Mo KANG ,  Moon Seung YANG ,  Jongryeol YOO ,  Sihyung LEE ,  Sunguk JANG ,  Eunhye CHOI

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/08

Abstract: A semiconductor device includes a channel pattern including first and second semiconductor patterns stacked on a substrate, a gate electrode covering top and lateral surfaces of the channel pattern and extending in a first direction, and including a first gate segment between the first semiconductor pattern and the second semiconductor pattern, a gate spacer covering a lateral surface of the gate electrode and including an opening exposing the channel pattern, and a first source/drain pattern on a side of the gate spacer and in contact with the channel pattern through the opening, the first source/drain pattern including a sidewall center thickness at a height of the first gate segment and at a center of the opening, and a sidewall edge thickness at the height of the first gate segment and at an edge of the opening, the sidewall edge thickness being about 0.7 to 1 times the sidewall center thickness.

公开(公告)号：US20250098147A1

公开(公告)日：2025-03-20

申请号：US18828170

申请日：2024-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunghwan JANG ,  Wonhee CHOI ,  Jinbum KIM ,  Daejin NAM ,  Hyojin PARK ,  Sunguk JANG

IPC: H10B12/00

Abstract: A semiconductor device includes a substrate, a bit line extending in a first direction on the substrate, a first vertical channel pattern and a second vertical channel pattern on the bit line, a back gate electrode between the first vertical channel pattern and the second vertical channel pattern and extending in a second direction perpendicular to the first direction across the bit line, a first word line extending in the second direction from one side of the first vertical channel pattern, a second word line extending in the second direction from other side of the second vertical channel pattern, and a contact pattern connected to each of the first vertical channel pattern and the second vertical channel pattern. When viewed from a cross-sectional view, each of the first vertical channel pattern and the second vertical channel pattern have a trapezoidal shape with the long sides facing each other.