公开(公告)号：US20170162674A1

公开(公告)日：2017-06-08

申请号：US15355781

申请日：2016-11-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin Bum KIM ,  Kang Hun MOON ,  Choeun LEE ,  Kyung Yub JEON ,  Sujin JUNG ,  Haegeon JUNG ,  Yang XU

IPC: H01L29/66 ,  H01L21/306 ,  H01L21/02 ,  H01L29/08

CPC classification number: H01L29/66795 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/30604 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming an active pattern protruding orthogonally from a substrate; forming a preliminary gate structure on the active pattern to cross the active pattern; etching the active pattern to form preliminary recess regions at both sides of the preliminary gate structure, wherein each of the preliminary recess regions is formed to define a delta region in an upper portion of the active pattern; forming a sacrificial layer on inner side surfaces and a bottom surface of the active pattern exposed by each of the preliminary recess regions; etching the delta regions and the sacrificial layer to form recess regions having a ‘U’-shaped section; and forming source/drain regions in the recess regions.

公开(公告)号：US20180151705A1

公开(公告)日：2018-05-31

申请号：US15871479

申请日：2018-01-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： JinBum KIM ,  Kang Hun MOON ,  Choeun LEE ,  Sujin JUNG ,  Yang XU

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/823425 ,  H01L21/823431 ,  H01L29/0657 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7848

Abstract: Methods of forming an integrated circuit device are provided. The methods may include forming a gate structure on a substrate, forming a first etch mask on a sidewall of the gate structure, anisotropically etching the substrate using the gate structure and the first etch mask as an etch mask to form a preliminary recess in the substrate, forming a sacrificial layer in the preliminary recess, forming a second etch mask on the first etch mask, etching the sacrificial layer and the substrate beneath the sacrificial layer using the gate structure and the first and second etch masks as an etch mask to form a source/drain recess in the substrate, and forming a source/drain in the source/drain recess. A sidewall of the source/drain recess may be recessed toward the gate structure relative to an outer surface of the second etch mask.

公开(公告)号：US20230387206A1

公开(公告)日：2023-11-30

申请号：US18117262

申请日：2023-03-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Hwan KIM ,  Kyung Ho KIM ,  Kang Hun MOON ,  Cho Eun LEE ,  Yong Uk JEON

IPC: H01L29/08 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/775 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4991 ,  H01L29/775 ,  H01L29/66545 ,  H01L29/66439

Abstract: A semiconductor device comprises an active pattern including a lower pattern and a plurality of sheet patterns that are spaced apart from the lower pattern in a first direction, a plurality of gate structures disposed on the lower pattern to be spaced apart from each other in a second direction, each of the gate structures including a gate electrode and gate insulating films, source/drain recesses defined between adjacent gate structures and a source/drain pattern filling the source/drain recesses. Each source/drain pattern may include a first semiconductor liner, which extend along sidewalls and a bottom surface of the source/drain recesses, second semiconductor liners, which are on the first semiconductor liners and extend along the sidewalls and the bottom surface of the source/drain recesses, and a filling semiconductor film, which is on the second semiconductor liners and fills the source/drain recess. The second semiconductor liners may be doped with carbon, and the first semiconductor liners may be in contact with the lower pattern and the sheet patterns, while the first semiconductor liners may include carbon-undoped regions.

公开(公告)号：US20180096845A1

公开(公告)日：2018-04-05

申请号：US15595945

申请日：2017-05-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cho Eun LEE ,  Jin Bum KIM ,  Kang Hun MOON ,  Jae Myung CHOE ,  Sun Jung KIM ,  Dong Suk SHIN ,  IL GYOU SHIN ,  Jeong Ho YOO

IPC: H01L21/02 ,  H01L21/223 ,  H01L29/66

CPC classification number: H01L21/02661 ,  H01L21/02071 ,  H01L21/223 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795

Abstract: A method of fabricating a semiconductor device is provided. The method includes forming a dummy gate electrode on a substrate, forming a trench on a side surface of the dummy gate electrode, performing a bake process of removing an impurity from the trench and forming a source/drain in the trench, wherein the bake process comprises a first stage and a second stage following the first stage, an air pressure in which the substrate is disposed during the first stage is different from an air pressure in which the substrate is disposed during the second stage, and the bake process is performed while the substrate is on a stage rotating the substrate, wherein a revolution per minute (RPM) of the substrate during the first stage is different from a revolution per minute (RPM) of the substrate during the second stage.

公开(公告)号：US20160359021A1

公开(公告)日：2016-12-08

申请号：US15134556

申请日：2016-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： JinBum KIM ,  Kang Hun MOON ,  Choeun LEE ,  Sujin JUNG ,  Yang XU

IPC: H01L29/66 ,  H01L29/08 ,  H01L21/306 ,  H01L29/06 ,  H01L21/308 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/66795 ,  H01L21/823425 ,  H01L21/823431 ,  H01L29/0657 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7848

Abstract: Methods of forming an integrated circuit device are provided. The methods may include forming a gate structure on a substrate, forming a first etch mask on a sidewall of the gate structure, anisotropically etching the substrate using the gate structure and the first etch mask as an etch mask to form a preliminary recess in the substrate, forming a sacrificial layer in the preliminary recess, forming a second etch mask on the first etch mask, etching the sacrificial layer and the substrate beneath the sacrificial layer using the gate structure and the first and second etch masks as an etch mask to form a source/drain recess in the substrate, and forming a source/drain in the source/drain recess. A sidewall of the source/drain recess may be recessed toward the gate structure relative to an outer surface of the second etch mask.

Abstract translation: 提供了形成集成电路器件的方法。 所述方法可以包括在衬底上形成栅极结构，在栅极结构的侧壁上形成第一蚀刻掩模，使用栅极结构和第一蚀刻掩模各向异性蚀刻衬底作为蚀刻掩模，以在衬底中形成预备凹槽 在所述初步凹槽中形成牺牲层，在所述第一蚀刻掩模上形成第二蚀刻掩模，使用所述栅极结构和所述第一和第二蚀刻掩模作为蚀刻掩模蚀刻所述牺牲层和所述牺牲层下方的所述衬底，以形成 源极/漏极凹部，并且在源极/漏极凹部中形成源极/漏极。 源极/漏极凹部的侧壁可以相对于第二蚀刻掩模的外表面朝向栅极结构凹陷。