公开(公告)号：US20170148797A1

公开(公告)日：2017-05-25

申请号：US15351739

申请日：2016-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Bum KIM ,  Myung-Gil KANG ,  Kang-Hun MOON ,  Cho-Eun LEE ,  Su-Jin JUNG ,  Min-Hee CHOI ,  Yang XU ,  Dong-Suk SHIN ,  Kwan-Heum LEE ,  Hoi-Sung CHUNG

IPC: H01L27/11 ,  H01L29/45 ,  H01L29/161 ,  H01L23/528 ,  H01L27/088 ,  H01L29/08

CPC classification number: H01L27/1104 ,  H01L21/823431 ,  H01L23/485 ,  H01L23/5283 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/66545 ,  H01L29/7848

Abstract: A semiconductor device may include a first active fin, a plurality of second active fins, a first source/drain layer structure, and a second source/drain layer structure. The first active fin may be on a first region of a substrate. The second active fins may be on a second region of the substrate. The first and second gate structures may be on the first and second active fins, respectively. The first source/drain layer structure may be on a portion of the first active fin that is adjacent to the first gate structure. The second source/drain layer structure may commonly contact upper surfaces of the second active fins adjacent to the second gate structure. A top surface of the second source/drain layer structure may be further from the surface of the substrate than a top surface of the first source/drain layer structure is to the surface of the substrate.

公开(公告)号：US20220415905A1

公开(公告)日：2022-12-29

申请号：US17929513

申请日：2022-09-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Bum KIM ,  Myung-Gil KANG ,  Kang-Hun MOON ,  Cho-Eun LEE ,  Su-Jin JUNG ,  Min-Hee CHOI ,  Yang XU ,  Dong-Suk SHIN ,  Kwan-Heum LEE ,  Hoi-Sung CHUNG

IPC: H01L27/11 ,  H01L23/528 ,  H01L29/66 ,  H01L27/088 ,  H01L29/161 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/78 ,  H01L29/45 ,  H01L29/417 ,  H01L23/485 ,  H01L27/092 ,  H01L29/165

Abstract: A semiconductor device may include a first active fin, a plurality of second active fins, a first source/drain layer structure, and a second source/drain layer structure. The first active fin may be on a first region of a substrate. The second active fins may be on a second region of the substrate. The first and second gate structures may be on the first and second active fins, respectively. The first source/drain layer structure may be on a portion of the first active fin that is adjacent to the first gate structure. The second source/drain layer structure may commonly contact upper surfaces of the second active fins adjacent to the second gate structure. A top surface of the second source/drain layer structure may be further from the surface of the substrate than a top surface of the first source/drain layer structure is to the surface of the substrate.

公开(公告)号：US20150162332A1

公开(公告)日：2015-06-11

申请号：US14543140

申请日：2014-11-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Bum KIM ,  Bon-Young KOO ,  Seok-Hoon KIM ,  Chul KIM ,  Kwan-Heum LEE ,  Byeong-Chan LEE ,  Su-Jin JUNG

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L29/161

CPC classification number: H01L27/0886 ,  H01L29/0653 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/785

Abstract: An integrated circuit device includes an electrically conductive pattern on a substrate. This electrically conductive pattern may be a gate pattern of a field effect transistor. A first electrically insulating spacer is provided on a sidewall of the electrically conductive pattern. The first electrically insulating spacer includes a first lower spacer and a first upper spacer, which extends on the first lower spacer and has a side surface vertically aligned with a corresponding side surface of the first lower spacer. The first upper spacer has a greater dielectric constant relative to a dielectric constant of the first lower spacer. A pair of parallel channel regions may also be provided, which protrude from a surface of the substrate. The electrically conductive pattern may surround top and side surfaces of the pair of parallel channel regions.

Abstract translation: 集成电路器件包括在衬底上的导电图案。 该导电图案可以是场效应晶体管的栅极图案。 第一电绝缘垫片设置在导电图案的侧壁上。 第一电绝缘间隔件包括第一下间隔件和第一上间隔件，其在第一下间隔件上延伸并且具有与第一下间隔件的对应侧表面垂直对准的侧表面。 第一上间隔物相对于第一下间隔物的介电常数具有更大的介电常数。 还可以设置一对平行的通道区域，其从衬底的表面突出。 导电图案可以围绕该对平行通道区域的顶表面和侧表面。

公开(公告)号：US20160293750A1

公开(公告)日：2016-10-06

申请号：US15049859

申请日：2016-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Bum KIM ,  Nam Kyu KIM ,  Hyun-Ho NOH ,  Dong-Chan SUH ,  Byeong-Chan LEE ,  Su-Jin JUNG ,  Jin-Yeong JOE ,  Bon-Young KOO

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/16

CPC classification number: H01L29/785 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7848 ,  H01L29/7856

Abstract: A semiconductor device includes an active fin structure extending in a first direction, the active fin structure including protruding portions divided by a recess, a plurality of gate structures extending in a second direction crossing the first direction and covering the protruding portions of the active fin structure, a first epitaxial pattern in a lower portion of the recess between the gate structures, a second epitaxial pattern on a portion of the first epitaxial pattern, the second epitaxial pattern contacting a sidewall of the recess, and a third epitaxial pattern on the first and second epitaxial patterns, the third epitaxial pattern filling the recess. The first epitaxial pattern includes a first impurity region having a first doping concentration, the second epitaxial pattern includes a second impurity region having a second doping concentration lower than the a first doping concentration, and the third epitaxial pattern includes a third impurity region having a third doping concentration higher than the second doping concentration. The semiconductor device may have good electrical characteristics.

Abstract translation: 半导体器件包括沿第一方向延伸的有源鳍结构，所述有源鳍结构包括由凹部分隔的突出部分，沿与第一方向交叉的第二方向延伸并覆盖有源鳍结构的突出部分的多个栅极结构 ，在栅极结构之间的凹部的下部中的第一外延图案，在第一外延图案的一部分上的第二外延图案，第二外延图案接触凹槽的侧壁，以及在第一外延图案的第一和第二外延图案 第二外延图案，填充凹槽的第三外延图案。 第一外延图案包括具有第一掺杂浓度的第一杂质区，第二外延图案包括具有低于第一掺杂浓度的第二掺杂浓度的第二杂质区，并且第三外延图包括具有第三掺杂浓度的第三杂质区 掺杂浓度高于第二掺杂浓度。 半导体器件可具有良好的电特性。

公开(公告)号：US20150194523A1

公开(公告)日：2015-07-09

申请号：US14149153

申请日：2014-01-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Bum KIM

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device is provided. At least two active fins protrude from a substrate. A gate pattern crosses the at least two active fins, covering part of each active fin. A seed layer is disposed on other part of the each active fin. The other part of the each active fin is not covered with the gate pattern. An epitaxial layer is disposed on the seed layer.

Abstract translation: 提供半导体器件。 至少两个活性翅片从基底突出。 栅极图案穿过至少两个活动鳍片，覆盖每个活动鳍片的一部分。 种子层设置在每个活性鳍片的另一部分上。 每个活动鳍片的另一部分不被栅极图案覆盖。 外延层设置在种子层上。

公开(公告)号：US20140264597A1

公开(公告)日：2014-09-18

申请号：US13839870

申请日：2013-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Bum KIM ,  Suk-Hun Choi

IPC: H01L27/12 ,  H01L21/76

CPC classification number: H01L21/76 ,  H01L21/76224 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: To fabricate a semiconductor device, a fin is formed to protrude from a substrate. The fin is extended in a first direction. A gate line is formed on the fin and the substrate. The gate line is extended in a second direction crossing the first direction. An amorphous material layer is conformally formed to cover the substrate, the fin, and the gate line. The amorphous material layer is partially removed, thereby forming a first remaining amorphous layer on side walls of the fin and a second remaining amorphous layer on side walls of the gate line. The first remaining amorphous layer and the second remaining amorphous layer are annealed and the first remaining amorphous material layer and the second remaining amorphous material layer are crystallized into a monocrystalline material layer and a polycrystalline material layer, respectively. The polycrystalline material layer is removed.

Abstract translation: 为了制造半导体器件，形成从基板突出的翅片。 翅片沿第一个方向延伸。 在翅片和基板上形成栅极线。 栅极线在与第一方向交叉的第二方向上延伸。 保形地形成无定形材料层以覆盖基板，翅片和栅极线。 部分去除非晶材料层，从而在翅片的侧壁上形成第一剩余非晶层，在栅极线的侧壁上形成第二剩余非晶层。 第一剩余非晶层和第二剩余非晶层退火，并且第一剩余非晶态材料层和第二剩余非晶态材料层分别结晶成单晶材料层和多晶材料层。 去除多晶材料层。