公开(公告)号：US09099314B2

公开(公告)日：2015-08-04

申请号：US12827506

申请日：2010-06-30

Applicant: Gurtej S. Sandhu ,  Kirk D. Prall

Inventor： Gurtej S. Sandhu ,  Kirk D. Prall

IPC: H01L21/3213 ,  H01L21/033 ,  H01L21/308 ,  H01L21/3205

CPC classification number: H01L21/67063 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/32053 ,  H01L21/32134

Abstract: Spacers in a pitch multiplication process are formed without performing a spacer etch. Rather, the mandrels are formed over a substrate and then the sides of the mandrels are reacted, e.g., in an oxidization, nitridation, or silicidation step, to form a material that can be selectively removed relative to the unreacted portions of the mandrel. The unreacted portions are selectively removed to leave a pattern of free-standing spacers. The free-standing spacers can serve as a mask for subsequent processing steps, such as etching the substrate.

Abstract translation: 在不执行间隔物蚀刻的情况下形成间距倍增过程中的间隔物。 相反，心轴形成在衬底上，然后心轴的侧面例如在氧化，氮化或硅化步骤中反应，以形成相对于心轴的未反应部分可以选择性去除的材料。 选择性地去除未反应部分以留下独立间隔物的图案。 独立的间隔物可以用作后续处理步骤的掩模，例如蚀刻基底。

公开(公告)号：US08999492B2

公开(公告)日：2015-04-07

申请号：US12026214

申请日：2008-02-05

Applicant: Dan B. Millward ,  Gurtej S. Sandhu

Inventor： Dan B. Millward ,  Gurtej S. Sandhu

IPC: G03G7/00 ,  B05D5/02 ,  C08F2/46 ,  C03C25/68 ,  G03F7/00 ,  B81C99/00 ,  B82Y10/00 ,  B05D1/28 ,  B82Y30/00 ,  B82Y40/00

CPC classification number: B41N1/08 ,  B05D1/283 ,  B41N3/036 ,  B81C99/009 ,  B81C2201/0149 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  G03F7/0002 ,  G03F7/0017 ,  Y02C20/30 ,  Y10T428/24802

Abstract: Methods for fabricating stamps and systems for patterning a substrate, and devices resulting from those methods are provided.

Abstract translation: 提供用于制造用于图案化衬底的印记和系统的方法以及由这些方法产生的器件。

公开(公告)号：US08946903B2

公开(公告)日：2015-02-03

申请号：US12833074

申请日：2010-07-09

Applicant: Gurtej S. Sandhu

Inventor： Gurtej S. Sandhu

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01B13/00 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/53276 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/76865 ,  H01L21/76877 ,  H01L23/53209 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments include electrical interconnects. The interconnects may contain laminate structures having a graphene region sandwiched between non-graphene regions. In some embodiments the graphene and non-graphene regions may be nested within one another. In some embodiments an electrically insulative material may be over an upper surface of the laminate structure, and an opening may extend through the insulative material to a portion of the laminate structure. Electrically conductive material may be within the opening and in electrical contact with at least one of the non-graphene regions of the laminate structure. Some embodiments include methods of forming electrical interconnects in which non-graphene material and graphene are alternately formed within a trench to form nested non-graphene and graphene regions.

Abstract translation: 一些实施例包括电互连。 互连可以包含层压结构，其具有夹在非石墨烯区域之间的石墨烯区域。 在一些实施例中，石墨烯和非石墨烯区域可以彼此嵌套。 在一些实施例中，电绝缘材料可以在层压结构的上表面之上，并且开口可以延伸穿过绝缘材料到层压结构的一部分。 导电材料可以在开口内并且与层压结构的非石墨烯区域中的至少一个电接触。 一些实施例包括形成电互连的方法，其中在沟槽内交替形成非石墨烯材料和石墨烯以形成嵌套的非石墨烯和石墨烯区域。

公开(公告)号：US08923038B2

公开(公告)日：2014-12-30

申请号：US13527173

申请日：2012-06-19

Applicant: Witold Kula ,  Gurtej S. Sandhu ,  Stephen J. Kramer

Inventor： Witold Kula ,  Gurtej S. Sandhu ,  Stephen J. Kramer

IPC: G11C11/15 ,  G11C11/00 ,  H01L29/82

CPC classification number: H01L43/08 ,  G11C11/161 ,  H01L27/228 ,  H01L43/02 ,  H01L43/12

Abstract: Methods of forming magnetic memory cells are disclosed. Magnetic and non-magnetic materials are formed into a primal precursor structure in an initial stress state of essentially no strain, compressive strain, or tensile strain. A stress-compensating material, e.g., a non-sacrificial, conductive material, is formed to be disposed on the primal precursor structure to form a stress-compensated precursor structure in a net beneficial stress state. Thereafter, the stress-compensated precursor structure may be patterned to form a cell core of a memory cell. The net beneficial stress state of the stress-compensated precursor structure lends to formation of one or more magnetic regions, in the cell core, exhibiting a vertical magnetic orientation without deteriorating a magnetic strength of the one or more magnetic regions. Also disclosed are memory cells, memory cell structures, semiconductor device structures, and spin torque transfer magnetic random access memory (STT-MRAM) systems.

Abstract translation: 公开了形成磁存储器单元的方法。 磁性和非磁性材料在基本上没有应变，压缩应变或拉伸应变的初始应力状态下形成原始前体结构。 形成应力补偿材料，例如非牺牲导电材料，以设置在原始前体结构上以在净有益应力状态下形成应力补偿前体结构。 此后，应力补偿前体结构可以被图案化以形成存储单元的单元芯。 应力补偿前体结构的净有益应力状态有助于在电池芯中形成一个或多个磁性区域，呈现垂直磁性取向而不会使一个或多个磁性区域的磁强度恶化。 还公开了存储器单元，存储单元结构，半导体器件结构和自旋转矩传递磁随机存取存储器（STT-MRAM）系统。

公开(公告)号：US08772841B2

公开(公告)日：2014-07-08

申请号：US13616307

申请日：2012-09-14

Applicant: D.V. Nirmal Ramaswamy ,  Gurtej S. Sandhu

Inventor： D.V. Nirmal Ramaswamy ,  Gurtej S. Sandhu

IPC: H01L29/66 ,  H01L29/94 ,  H01L21/70 ,  H01L27/108

CPC classification number: H01L45/08 ,  G11C13/0007 ,  H01L45/145 ,  H01L45/165

Abstract: Methods, devices, and systems associated with oxide based memory can include a method of forming an oxide based memory cell. Forming an oxide based memory cell can include forming a first conductive element, forming an oxide over the first conductive element, implanting a reactive metal into the oxide, and forming a second conductive element over the oxide.

Abstract translation: 与基于氧化物的存储器相关联的方法，装置和系统可以包括形成基于氧化物的存储器单元的方法。 形成基于氧化物的存储单元可以包括形成第一导电元件，在第一导电元件上形成氧化物，将活性金属注入到氧化物中，以及在氧化物上形成第二导电元件。

公开(公告)号：US08686535B2

公开(公告)日：2014-04-01

申请号：US12758488

申请日：2010-04-12

Applicant: Gurtej S. Sandhu ,  John A. Smythe, III

Inventor： Gurtej S. Sandhu ,  John A. Smythe, III

IPC: H01L21/70

CPC classification number: H01L21/76237 ,  G11C11/401 ,  H01L27/10844 ,  H01L27/11517

Abstract: Embodiments of the disclosure include a shallow trench isolation structure having a dielectric material with energetic species implanted to a predetermined depth of the dielectric material. Embodiments further include methods of fabricating the trench structures with the implant of energetic species to the predetermined depth. In various embodiments the implant of energetic species is used to densify the dielectric material to provide a uniform wet etch rate across the surface of the dielectric material. Embodiments also include memory devices, integrated circuits, and electronic systems that include shallow trench isolation structures having the dielectric material with the high flux of energetic species implanted to the predetermined depth of the dielectric material.

Abstract translation: 本公开的实施例包括浅沟槽隔离结构，其具有将能量物质注入电介质材料的预定深度的电介质材料。 实施例还包括使能量物质的植入物到预定深度制造沟槽结构的方法。 在各种实施例中，能量物质的注入用于致密化电介质材料，以提供穿过电介质材料表面的均匀的湿蚀刻速率。 实施例还包括存储器件，集成电路和电子系统，其包括浅沟槽隔离结构，其具有植入到介电材料的预定深度的高能量物质的高通量的电介质材料。

公开(公告)号：US08673787B2

公开(公告)日：2014-03-18

申请号：US13164970

申请日：2011-06-21

Applicant: Gurtej S. Sandhu ,  Max F. Hineman ,  Daniel A. Steckert ,  Jingyi Bai ,  Shane J. Trapp ,  Tony Schrock

Inventor： Gurtej S. Sandhu ,  Max F. Hineman ,  Daniel A. Steckert ,  Jingyi Bai ,  Shane J. Trapp ,  Tony Schrock

IPC: H01L21/302

CPC classification number: H01L21/76802 ,  H01L21/31116 ,  Y10S438/906

Abstract: A method of high aspect ratio contact etching a substantially vertical contact hole in an oxide layer using a hard photoresist mask is described. The oxide layer is deposited on an underlying substrate. A plasma etching gas is formed from a carbon source gas. Dopants are mixed into the gas. The doped plasma etching gas etches a substantially vertical contact hole through the oxide layer by doping carbon chain polymers formed along the sidewalls of the contact holes during the etching process into a conductive state. The conductive state of the carbon chain polymers reduces the charge buildup along sidewalls to prevent twisting of the contact holes by bleeding off the charge and ensuring proper alignment with active area landing regions. The etching stops at the underlying substrate.

Abstract translation: 描述了使用硬光致抗蚀剂掩模的高纵横比接触蚀刻氧化物层中的基本上垂直的接触孔的方法。 氧化物层沉积在下面的衬底上。 由碳源气体形成等离子体蚀刻气体。 掺杂剂混入气体中。 掺杂的等离子体蚀刻气体通过将在蚀刻过程中沿着接触孔的侧壁形成的碳链聚合物掺杂到导电状态来蚀刻通过氧化物层的基本垂直的接触孔。 碳链聚合物的导电状态减少了沿着侧壁的电荷累积，以防止通过渗出电荷并确保与有源区着陆区域的适当对准来接合孔的扭曲。 蚀刻停止在下面的基底。

公开(公告)号：US08664112B2

公开(公告)日：2014-03-04

申请号：US13085122

申请日：2011-04-12

Applicant: Gurtej S. Sandhu ,  Nishant Sinha ,  John A. Smythe

Inventor： Gurtej S. Sandhu ,  Nishant Sinha ,  John A. Smythe

IPC: H01L23/52

CPC classification number: H01L23/5283 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/5329 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/105 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices comprise at least one integrated circuit layer, at least one conductive trace and an insulative material adjacent at least a portion of the at least one conductive trace. At least one interconnect structure extends through a portion of the at least one conductive trace and a portion of the insulative material, the at least one interconnect structure comprising a transverse cross-sectional dimension through the at least one conductive trace which differs from a transverse cross-sectional dimension through the insulative material. Methods of forming semiconductor devices comprising at least one interconnect structure are also disclosed.

Abstract translation: 半导体器件包括至少一个集成电路层，至少一个导电迹线和与至少一个导电迹线的至少一部分相邻的绝缘材料。 至少一个互连结构延伸穿过所述至少一个导电迹线的一部分和所述绝缘材料的一部分，所述至少一个互连结构包括穿过所述至少一个导电迹线的横向截面尺寸，所述导电迹线与横向交叉不同 通过绝缘材料的尺寸。 还公开了形成包括至少一个互连结构的半导体器件的方法。

公开(公告)号：US20140054709A1

公开(公告)日：2014-02-27

申请号：US13595832

申请日：2012-08-27

Applicant: D. V. Nirmal Ramaswamy ,  Gurtej S. Sandhu

Inventor： D. V. Nirmal Ramaswamy ,  Gurtej S. Sandhu

IPC: H01L29/78 ,  H01L27/088

CPC classification number: H01L29/7887 ,  H01L27/11521

Abstract: A transistor device includes a pair of source/drain regions having a channel region there-between. A first gate is proximate the channel region. A gate dielectric is between the first gate and the channel region. A second gate is proximate the channel region. A programmable material is between the second gate and the channel region. The programmable material includes at least one of a) a multivalent metal oxide portion and an oxygen-containing dielectric portion, or b) a multivalent metal nitride portion and a nitrogen-containing dielectric portion. Memory cells and arrays of memory cells are disclosed.

Abstract translation: 晶体管器件包括在其之间具有沟道区的一对源/漏区。 第一个门靠近通道区域。 栅介质位于第一栅极和沟道区之间。 第二个门靠近通道区域。 可编程材料位于第二栅极和沟道区域之间。 可编程材料包括a）多价金属氧化物部分和含氧电介质部分中的至少一种，或b）多价金属氮化物部分和含氮介电部分。 公开了存储器单元和存储器单元阵列。

公开(公告)号：US08643087B2

公开(公告)日：2014-02-04

申请号：US11524343

申请日：2006-09-20

Applicant: Gurtej S. Sandhu ,  Chandra Mouli

Inventor： Gurtej S. Sandhu ,  Chandra Mouli

IPC: H01L29/10

CPC classification number: H01L27/108 ,  B82Y10/00 ,  G11C11/24 ,  H01L27/10808 ,  H01L27/10844 ,  H01L27/10873 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/42392 ,  H01L29/78642 ,  H01L51/057

Abstract: Methods and structures are described for reducing leakage currents in semiconductor memory storage cells. Vertically oriented nanorods may be used in the channel region of an access transistor. The nanorod diameter can be made small enough to cause an increase in the electronic band gap energy in the channel region of the access transistor, which may serve to limit channel leakage currents in its off-state. In various embodiments, the access transistor may be electrically coupled to a double-sided capacitor. Memory devices according to embodiments of the invention, and systems including such devices are also disclosed.

Abstract translation: 描述了用于减少半导体存储器存储单元中的漏电流的方法和结构。 垂直取向的纳米棒可用于存取晶体管的沟道区。 纳米棒直径可以做得足够小以引起存取晶体管的沟道区域中的电子带隙能量的增加，这可能有助于将通道漏电流限制在其截止状态。 在各种实施例中，存取晶体管可以电耦合到双面电容器。 还公开了根据本发明的实施例的存储器件，以及包括这种器件的系统。