知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

391 records (took 0.03 seconds)

    Diodes, and Methods of Forming Diodes
    1.
    发明申请
    Diodes, and Methods of Forming Diodes 有权
    二极管和形成二极管的方法

    公开(公告)号：US20110068325A1

    公开(公告)日：2011-03-24

    申请号：US12953776

    申请日：2010-11-24

    Applicant: Gurtej S. Sandhu ,  Chandra Mouli

    Inventor： Gurtej S. Sandhu ,  Chandra Mouli

    IPC: H01L29/88 ,  H01L21/28

    CPC classification number: H01L29/66151 ,  B82Y10/00 ,  H01L21/28 ,  H01L21/283 ,  H01L28/90 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66143 ,  H01L29/872 ,  H01L29/88 ,  H01L45/00

    Abstract: Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is deposited along an undulating topography that extends across the pedestal and base, and a second electrode is formed over the least one layer. The first electrode, at least one layer, and second electrode together form a structure that conducts current between the first and second electrodes when voltage of one polarity is applied to the structure, and that inhibits current flow between the first and second electrodes when voltage having a polarity opposite to said one polarity is applied to the structure. Some embodiments include diodes having a first electrode that contains two or more projections extending upwardly from a base, having at least one layer over the first electrode, and having a second electrode over the at least one layer.

    Abstract translation: 一些实施例包括形成二极管的方法，其中第一电极形成为具有从基部向上延伸的基座。 沿着延伸穿过基座和基底的波状形貌沉积至少一层，并且在最少一层上形成第二电极。 第一电极，至少一层和第二电极一起形成当一个极性的电压施加到结构时在第一和第二电极之间传导电流的结构，并且当电压具有 与所述一个极性相反的极性被施加到该结构。 一些实施例包括具有第一电极的二极管，该第一电极包含从基底向上延伸的两个或更多个突起，在第一电极上具有至少一个层，并且在该至少一个层上具有第二电极。

    Methods of cooling semiconductor dies
    2.
    发明申请
    Methods of cooling semiconductor dies 有权
    冷却半导体管芯的方法

    公开(公告)号：US20100302740A1

    公开(公告)日：2010-12-02

    申请号：US12855562

    申请日：2010-08-12

    Applicant: Chandra Mouli ,  Gurtej S. Sandhu

    Inventor： Chandra Mouli ,  Gurtej S. Sandhu

    IPC: H05K7/20 ,  H01L21/50 ,  F28D15/00

    CPC classification number: H01L23/3672 ,  H01L23/367 ,  H01L23/373 ,  H01L23/3733 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/10158 ,  Y10S977/742

    Abstract: The invention includes semiconductor packages having grooves within a semiconductor die backside; and includes semiconductor packages utilizing carbon nanostructures (such as, for example, carbon nanotubes) as thermally conductive interface materials. The invention also includes methods of cooling a semiconductor die in which coolant is forced through grooves in a backside of the die, and includes methods of making semiconductor packages.

    Abstract translation: 本发明包括在半导体模具背面内具有凹槽的半导体封装; 并且包括使用碳纳米结构（例如，碳纳米管）作为导热界面材料的半导体封装。 本发明还包括冷却半导体管芯的方法，其中冷却剂被迫通过管芯背面的凹槽，并且包括制造半导体封装件的方法。

    Diodes, and Methods of Forming Diodes
    3.
    发明申请
    Diodes, and Methods of Forming Diodes 有权
    二极管和形成二极管的方法

    公开(公告)号：US20090315020A1

    公开(公告)日：2009-12-24

    申请号：US12141265

    申请日：2008-06-18

    Applicant: Gurtej S. Sandhu ,  Chandra Mouli

    Inventor： Gurtej S. Sandhu ,  Chandra Mouli

    IPC: H01L29/88 ,  H01L21/329

    CPC classification number: H01L29/66151 ,  B82Y10/00 ,  H01L21/28 ,  H01L21/283 ,  H01L28/90 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66143 ,  H01L29/872 ,  H01L29/88 ,  H01L45/00

    Abstract: Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is deposited along an undulating topography that extends across the pedestal and base, and a second electrode is formed over the least one layer. The first electrode, at least one layer, and second electrode together form a structure that conducts current between the first and second electrodes when voltage of one polarity is applied to the structure, and that inhibits current flow between the first and second electrodes when voltage having a polarity opposite to said one polarity is applied to the structure. Some embodiments include diodes having a first electrode that contains two or more projections extending upwardly from a base, having at least one layer over the first electrode, and having a second electrode over the at least one layer.

    Abstract translation: 一些实施例包括形成二极管的方法，其中第一电极形成为具有从基部向上延伸的基座。 沿着延伸穿过基座和基底的波状形貌沉积至少一层，并且在最少一层上形成第二电极。 第一电极，至少一层和第二电极一起形成当一个极性的电压施加到结构时在第一和第二电极之间传导电流的结构，并且当电压具有 与所述一个极性相反的极性被施加到该结构。 一些实施例包括具有第一电极的二极管，该第一电极包含从基底向上延伸的两个或更多个突起，在第一电极上具有至少一个层，并且在该至少一个层上具有第二电极。

    Methods of forming semiconductor package
    4.
    发明授权
    Methods of forming semiconductor package 有权
    形成半导体封装的方法

    公开(公告)号：US07494910B2

    公开(公告)日：2009-02-24

    申请号：US11370093

    申请日：2006-03-06

    Applicant: Chandra Mouli ,  Gurtej S. Sandhu

    Inventor： Chandra Mouli ,  Gurtej S. Sandhu

    IPC: H01L21/44

    CPC classification number: H01L23/3672 ,  H01L23/367 ,  H01L23/373 ,  H01L23/3733 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/10158 ,  Y10S977/742

    Abstract: The invention includes semiconductor packages having grooves within a semiconductor die backside; and includes semiconductor packages utilizing carbon nanostructures (such as, for example, carbon nanotubes) as thermally conductive interface materials. The invention also includes methods of cooling a semiconductor die in which coolant is forced through grooves in a backside of the die, and includes methods of making semiconductor packages.

    Abstract translation: 本发明包括在半导体模具背面内具有凹槽的半导体封装; 并且包括使用碳纳米结构（例如，碳纳米管）作为导热界面材料的半导体封装。 本发明还包括冷却半导体管芯的方法，其中冷却剂被迫通过管芯背面的凹槽，并且包括制造半导体封装件的方法。

    SEMICONDUCTOR PACKAGES
    5.
    发明申请
    SEMICONDUCTOR PACKAGES 有权
    半导体封装

    公开(公告)号：US20120235310A1

    公开(公告)日：2012-09-20

    申请号：US13485853

    申请日：2012-05-31

    Applicant: Chandra Mouli ,  Gurtej S. Sandhu

    Inventor： Chandra Mouli ,  Gurtej S. Sandhu

    IPC: H01L23/498 ,  B82Y99/00

    CPC classification number: H01L23/3672 ,  H01L23/367 ,  H01L23/373 ,  H01L23/3733 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/10158 ,  Y10S977/742

    Abstract: The invention includes semiconductor packages having grooves within a semiconductor die backside; and includes semiconductor packages utilizing carbon nanostructures (such as, for example, carbon nanotubes) as thermally conductive interface materials. The invention also includes methods of cooling a semiconductor die in which coolant is forced through grooves in a backside of the die, and includes methods of making semiconductor packages.

    Abstract translation: 本发明包括在半导体模具背面内具有凹槽的半导体封装; 并且包括使用碳纳米结构（例如，碳纳米管）作为导热界面材料的半导体封装。 本发明还包括冷却半导体管芯的方法，其中冷却剂被迫通过管芯背面的凹槽，并且包括制造半导体封装件的方法。

    Reduced leakage memory cells
    6.
    发明授权
    Reduced leakage memory cells 有权
    减少泄漏记忆体

    公开(公告)号：US08643087B2

    公开(公告)日：2014-02-04

    申请号：US11524343

    申请日：2006-09-20

    Applicant: Gurtej S. Sandhu ,  Chandra Mouli

    Inventor： Gurtej S. Sandhu ,  Chandra Mouli

    IPC: H01L29/10

    CPC classification number: H01L27/108 ,  B82Y10/00 ,  G11C11/24 ,  H01L27/10808 ,  H01L27/10844 ,  H01L27/10873 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/42392 ,  H01L29/78642 ,  H01L51/057

    Abstract: Methods and structures are described for reducing leakage currents in semiconductor memory storage cells. Vertically oriented nanorods may be used in the channel region of an access transistor. The nanorod diameter can be made small enough to cause an increase in the electronic band gap energy in the channel region of the access transistor, which may serve to limit channel leakage currents in its off-state. In various embodiments, the access transistor may be electrically coupled to a double-sided capacitor. Memory devices according to embodiments of the invention, and systems including such devices are also disclosed.

    Abstract translation: 描述了用于减少半导体存储器存储单元中的漏电流的方法和结构。 垂直取向的纳米棒可用于存取晶体管的沟道区。 纳米棒直径可以做得足够小以引起存取晶体管的沟道区域中的电子带隙能量的增加，这可能有助于将通道漏电流限制在其截止状态。 在各种实施例中，存取晶体管可以电耦合到双面电容器。 还公开了根据本发明的实施例的存储器件，以及包括这种器件的系统。

    Methods of cooling semiconductor dies
    7.
    发明授权
    Methods of cooling semiconductor dies 有权
    冷却半导体管芯的方法

    公开(公告)号：US08207016B2

    公开(公告)日：2012-06-26

    申请号：US12855562

    申请日：2010-08-12

    Applicant: Chandra Mouli ,  Gurtej S. Sandhu

    Inventor： Chandra Mouli ,  Gurtej S. Sandhu

    IPC: H01L21/00

    CPC classification number: H01L23/3672 ,  H01L23/367 ,  H01L23/373 ,  H01L23/3733 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/10158 ,  Y10S977/742

    Abstract: The invention includes semiconductor packages having grooves within a semiconductor die backside; and includes semiconductor packages utilizing carbon nanostructures (such as, for example, carbon nanotubes) as thermally conductive interface materials. The invention also includes methods of cooling a semiconductor die in which coolant is forced through grooves in a backside of the die, and includes methods of making semiconductor packages.

    Abstract translation: 本发明包括在半导体模具背面内具有凹槽的半导体封装; 并且包括使用碳纳米结构（例如，碳纳米管）作为导热界面材料的半导体封装。 本发明还包括冷却半导体管芯的方法，其中冷却剂被迫通过管芯背面的凹槽，并且包括制造半导体封装件的方法。

    Floating-gate structure with dielectric component
    8.
    发明授权
    Floating-gate structure with dielectric component 有权
    具有介质成分的浮栅结构

    公开(公告)号：US07485526B2

    公开(公告)日：2009-02-03

    申请号：US11155197

    申请日：2005-06-17

    Applicant: Chandra Mouli ,  Gurtej S. Sandhu

    Inventor： Chandra Mouli ,  Gurtej S. Sandhu

    IPC: H01L21/336 ,  H01L29/788

    CPC classification number: H01L29/7883 ,  B82Y10/00 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42332 ,  H01L29/66825

    Abstract: Floating-gate memory cells having a floating gate with a conductive portion and a dielectric portion facilitate increased levels of charge trapping sites within the floating gate. The conductive portion includes a continuous component providing bulk conductivity to the floating gate. The dielectric portion is discontinuous within the conductive portion and may include islands of dielectric material and/or one or more contiguous layers of dielectric material having discontinuities.

    Abstract translation: 具有带有导电部分和电介质部分的浮动栅极的浮栅存储器单元便于浮置栅极内的电荷俘获位置的增加。 导电部分包括向浮动栅极提供体导电性的连续部件。 电介质部分在导电部分内是不连续的，并且可以包括介电材料岛和/或具有不连续性的一个或多个相邻的电介质材料层。

    Methods of forming diodes
    10.
    发明授权
    Methods of forming diodes 有权
    形成二极管的方法

    公开(公告)号：US08889538B2

    公开(公告)日：2014-11-18

    申请号：US13599746

    申请日：2012-08-30

    Applicant: Gurtej S. Sandhu ,  Chandra Mouli

    Inventor： Gurtej S. Sandhu ,  Chandra Mouli

    IPC: H01L21/28 ,  H01L21/44 ,  H01L29/06 ,  H01L45/00 ,  H01L29/872 ,  H01L29/417 ,  H01L29/08 ,  H01L29/66 ,  B82Y10/00 ,  H01L49/02

    CPC classification number: H01L29/66151 ,  B82Y10/00 ,  H01L21/28 ,  H01L21/283 ,  H01L28/90 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66143 ,  H01L29/872 ,  H01L29/88 ,  H01L45/00

    Abstract: Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is deposited along an undulating topography that extends across the pedestal and base, and a second electrode is formed over the least one layer. The first electrode, at least one layer, and second electrode together form a structure that conducts current between the first and second electrodes when voltage of one polarity is applied to the structure, and that inhibits current flow between the first and second electrodes when voltage having a polarity opposite to said one polarity is applied to the structure. Some embodiments include diodes having a first electrode that contains two or more projections extending upwardly from a base, having at least one layer over the first electrode, and having a second electrode over the at least one layer.

    Abstract translation: 一些实施例包括形成二极管的方法，其中第一电极形成为具有从基部向上延伸的基座。 沿着延伸穿过基座和基底的波状形貌沉积至少一层，并且在最少一层上形成第二电极。 第一电极，至少一层和第二电极一起形成当一个极性的电压施加到结构时在第一和第二电极之间传导电流的结构，并且当电压具有 与所述一个极性相反的极性被施加到该结构。 一些实施例包括具有第一电极的二极管，该第一电极包含从基底向上延伸的两个或更多个突起，在第一电极上具有至少一个层，并且在该至少一个层上具有第二电极。

Patent Agency Ranking