公开(公告)号：US20180130704A1

公开(公告)日：2018-05-10

申请号：US15809120

申请日：2017-11-10

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Yong LI

IPC分类号： H01L21/768 ,  H01L21/02 ,  H01L29/45 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L21/76858 ,  H01L21/02164 ,  H01L21/02236 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76877 ,  H01L21/823443 ,  H01L21/823835 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53266 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/785

摘要： Semiconductor devices and fabrication methods thereof are provided. An exemplary fabrication method includes providing a base substrate; forming gate structures over the base substrate; forming doped source/drain regions in the base substrate at two sides of each of the gate structures; forming an oxide layer on each of the doped source/drain regions; forming a metal layer on the oxide layer; and performing a reactive thermal annealing process, such that the metal layer reacts with a material of the oxide layer and a material of the doped source/drain regions to form a metal contact layer on each of the doped source/drain regions. The metal contact layer includes a first metal contact layer on the doped source/drain region, an oxygen-containing metal contact layer on the first metal contact layer, and a second metal contact layer on the oxygen-containing metal contact layer.

公开(公告)号：US09966339B2

公开(公告)日：2018-05-08

申请号：US14290784

申请日：2014-05-29

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Hung Lin ,  Ching-Fu Yeh ,  Yu-Min Chang ,  You-Hua Chou ,  Chih-Wei Chang ,  Sheng-Hsuan Lin

IPC分类号： H01L21/4763 ,  H01L23/532 ,  H01L23/522 ,  H01L21/285 ,  H01L21/768

CPC分类号： H01L23/53233 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76873 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming an interconnect structure includes forming a dielectric layer overlying a substrate, forming an opening in the dielectric layer, forming a metal-containing layer overlying the opening in the dielectric layer, forming a conformal protective layer overlying the metal-containing layer, filling a conductive layer in the opening, and performing a thermal process to form a metal oxide layer barrier layer underlying the metal-containing layer.

公开(公告)号：US09966275B2

公开(公告)日：2018-05-08

申请号：US15381779

申请日：2016-12-16

申请人： Applied Materials, Inc.

发明人： Brent Biggs ,  Avgerinos V. Gelatos ,  Takashi Kuratomi ,  Mark H. Lee

IPC分类号： H01L21/3205

CPC分类号： H01L21/32053 ,  H01L21/28518 ,  H01L21/321 ,  H01L21/76862

摘要： Methods for reducing oxygen content in an oxidized annealed metal nitride film comprising exposing the film to a plasma.

公开(公告)号：US09960184B2

公开(公告)日：2018-05-01

申请号：US15645686

申请日：2017-07-10

申请人： GLOBALFOUNDRIES Inc.

发明人： Jan Hoentschel ,  Peter Baars ,  Hans-Peter Moll

IPC分类号： H01L27/12 ,  H01L29/94 ,  H01L27/06 ,  H01L21/762 ,  H01L21/84 ,  H01L29/786 ,  H01L49/02 ,  H01L29/06 ,  H01L21/265 ,  H01L21/285 ,  H01L27/108

CPC分类号： H01L27/1207 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/10829 ,  H01L27/1085 ,  H01L27/1087 ,  H01L28/60 ,  H01L29/0649 ,  H01L29/786 ,  H01L29/94

摘要： A semiconductor device includes a semiconductor-on-insulator (SOI) wafer having a semiconductor substrate, a buried insulating layer positioned above the semiconductor substrate, and a semiconductor layer positioned above the buried insulating layer. A shallow trench isolation (STI) structure is positioned in the SOI wafer and separates a first region of the SOI wafer from a second region of the SOI wafer, wherein the semiconductor layer is not present above the buried insulating layer in the first region, and wherein the buried insulating layer and the semiconductor layer are not present in at least a first portion of the second region adjacent to the STI structure. A dielectric layer is positioned above the buried insulating layer in the first region, and a conductive layer is positioned above the dielectric layer in the first region.

公开(公告)号：US09954067B2

公开(公告)日：2018-04-24

申请号：US14632412

申请日：2015-02-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Wei-Che Tsai ,  Hsin-Hung Chen

IPC分类号： H01L21/321 ,  H01L21/768 ,  H01L23/535 ,  H01L29/417 ,  H01L23/485 ,  H01L21/285 ,  H01L21/8234

CPC分类号： H01L29/41775 ,  H01L21/26506 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/321 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/485 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659

摘要： A semiconductor device includes a gate structure on a substrate; a protection layer on the gate structure; a source/drain region adjacent to the gate structure; and an interconnect plug on the source/drain region. The gate structure includes a gate electrode including a top surface; and a sidewall spacer interfacing a sidewall of the gate electrode. The protection layer covers at least a first portion of the top surface and the sidewall spacer. The protection layer is interposed between the interconnect plug and the gate electrode.

公开(公告)号：US09929234B2

公开(公告)日：2018-03-27

申请号：US15144842

申请日：2016-05-03

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chih-Kai Hsu ,  Ssu-I Fu ,  Yu-Hsiang Hung ,  Wei-Chi Cheng ,  Jyh-Shyang Jenq ,  Tsung-Mu Yang

IPC分类号： H01L21/02 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L23/535 ,  H01L21/768

CPC分类号： H01L29/0653 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/535 ,  H01L29/66795 ,  H01L29/785

摘要： A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a gate structure is formed on the substrate. Next, a recess is formed adjacent to two sides of the gate structure, and an epitaxial layer is formed in the recess, in which a top surface of the epitaxial layer is lower than a top surface of the substrate. Next, a cap layer is formed on the epitaxial layer, in which a top surface of the cap layer is higher than a top surface of the substrate.

公开(公告)号：US20180076065A1

公开(公告)日：2018-03-15

申请号：US15418506

申请日：2017-01-27

申请人： Applied Materials, Inc.

发明人： Xinyu BAO ,  Hua CHUNG ,  Schubert S. CHU

IPC分类号： H01L21/67 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/285 ,  H01J37/32 ,  C30B25/04 ,  C30B25/18 ,  C30B29/06 ,  B08B7/00

CPC分类号： H01L21/67207 ,  B08B7/0035 ,  C30B25/04 ,  C30B25/186 ,  C30B29/06 ,  H01J37/32458 ,  H01J37/32899 ,  H01J2237/334 ,  H01L21/02046 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/3065 ,  H01L21/67167 ,  H01L21/67184 ,  H01L21/67201 ,  H01L29/66636 ,  H01L29/66795

摘要： Implementations of the present disclosure generally relate to methods and apparatuses for epitaxial deposition on substrate surfaces. More particularly, implementations of the present disclosure generally relate to an integrated system for processing N-type metal-oxide semiconductor (NMOS) devices. In one implementation, a cluster tool for processing a substrate is provided. The cluster tool includes a pre-clean chamber, an etch chamber, one or more pass through chambers, one or more outgassing chambers, a first transfer chamber, a second transfer chamber, and one or more process chambers. The pre-clean chamber and the etch chamber are coupled to a first transfer chamber. The one or more pass through chambers are coupled to and disposed between the first transfer chamber and the second transfer chamber. The one or more outgassing chambers are coupled to the second transfer chamber. The one or more process chambers are coupled to the second transfer chamber.

公开(公告)号：US20180069123A1

公开(公告)日：2018-03-08

申请号：US15811577

申请日：2017-11-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsueh-Chang Sung ,  Kun-Mu Li ,  Tze-Liang Lee ,  Chii-Horng Li ,  Tsz-Mei Kwok

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/165

CPC分类号： H01L29/7848 ,  H01L21/02057 ,  H01L21/28 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/823425 ,  H01L27/088 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

摘要： An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region. The second silicon germanium region comprises a portion in the opening. The second silicon germanium region has a second germanium percentage greater than the first germanium percentage. A silicon cap substantially free from germanium is over the second silicon germanium region.

公开(公告)号：US20180068858A1

公开(公告)日：2018-03-08

申请号：US15801458

申请日：2017-11-02

申请人： International Business Machines Corporation ,  GlobalFoundries, Inc.

发明人： Kangguo Cheng ,  Ruilong Xie ,  Tenko Yamashita

IPC分类号： H01L21/285 ,  H01L21/283 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08

CPC分类号： H01L21/28518 ,  H01L21/283 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/7851 ,  H01L2029/7858

摘要： A method of making a semiconductor device includes forming a recessed fin in a substrate, the recessed fin being substantially flush with a surface of the substrate; performing an epitaxial growth process over the recessed fin to form a source/drain over the recessed fin; and disposing a conductive metal around the source/drain.

公开(公告)号：US09911846B2

公开(公告)日：2018-03-06

申请号：US15416805

申请日：2017-01-26

申请人： FUJI ELECTRIC CO., LTD.

发明人： Masanobu Iwaya ,  Makoto Utsumi

IPC分类号： H01L29/00 ,  H01L29/78 ,  H01L29/08 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/49 ,  H01L21/02 ,  H01L21/033 ,  H01L21/285 ,  H01L29/16

CPC分类号： H01L29/7827 ,  H01L21/02529 ,  H01L21/0334 ,  H01L21/28518 ,  H01L21/8238 ,  H01L21/823814 ,  H01L27/2454 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/4966 ,  H01L29/66068 ,  H01L29/665 ,  H01L29/66666 ,  H01L29/78 ,  H01L2924/13091

摘要： An interlayer insulating film is formed on a gate insulating film and a gate electrode, and the interlayer insulating film is opened forming contact holes. Next, the interlayer insulating film and regions exposed by the contact holes are covered by a titanium nitride film, and the titanium nitride film is etched to remain only at portions of the gate insulating film and the interlayer insulating film exposed in the contact holes. The interlayer insulating film and the regions exposed by the contact holes are covered by a nickel film, and after the nickel film directly contacting the interlayer insulating film 8 is removed, the nickel film is heat treated and a nickel silicide layer is formed.