公开(公告)号：US09935012B1

公开(公告)日：2018-04-03

申请号：US15361824

申请日：2016-11-28

申请人： GLOBALFOUNDRIES INC.

发明人： Jinsheng Gao ,  Haigou Huang

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/027 ,  H01L21/308 ,  H01L29/16 ,  H01L21/02

CPC分类号： H01L21/823431 ,  H01L21/3081 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823412 ,  H01L29/16 ,  H01L29/66795

摘要： Disclosed are methods of forming different shapes in different regions of a specific layer. In the methods, a first mask layer and an etch process are used to form first shapes in a first region. Subsequently, a second mask layer and additional etch process(es) are used to form second shapes in a second region. However, before the second shapes are formed, a sacrificial layer of a degradable material is deposited onto the first mask layer and within openings in the specific layer surrounding the first shapes, thereby protecting the first shapes during formation of the second shapes. After the second shapes are formed, the material of the sacrificial layer is degraded (e.g., oxidized, volatilized, burned-off, etc.) so as to selectively remove that material from surfaces of the first mask layer and the specific layer without impacting the profiles of either the first shapes or the second shapes.

公开(公告)号：US09929232B2

公开(公告)日：2018-03-27

申请号：US15414700

申请日：2017-01-25

申请人： FUJI ELECTRIC CO., LTD.

发明人： Tomonori Katano ,  Fumikazu Imai

IPC分类号： H01L29/00 ,  H01L29/06 ,  H01L29/16 ,  H01L29/20 ,  H01L21/265 ,  H01L21/04 ,  H01L21/324 ,  H01L21/67 ,  H01L29/167 ,  H01L29/861 ,  H01L29/36 ,  H01L29/872 ,  H01L29/78 ,  H01L29/739 ,  H01L29/66

CPC分类号： H01L29/0615 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02675 ,  H01L21/0415 ,  H01L21/046 ,  H01L21/26513 ,  H01L21/26546 ,  H01L21/268 ,  H01L21/2686 ,  H01L21/324 ,  H01L21/67115 ,  H01L29/0619 ,  H01L29/0688 ,  H01L29/16 ,  H01L29/1602 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/2003 ,  H01L29/36 ,  H01L29/6603 ,  H01L29/66045 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/66143 ,  H01L29/66212 ,  H01L29/66325 ,  H01L29/66333 ,  H01L29/66477 ,  H01L29/66522 ,  H01L29/66712 ,  H01L29/7393 ,  H01L29/7801 ,  H01L29/7811 ,  H01L29/861 ,  H01L29/872

摘要： An impurity of a second conductivity type is selectively doped in a surface of a semiconductor substrate of a first conductivity type to form doped regions. A portion of a surface of the doped regions is covered by a heat insulating film. At least a remaining portion of the surface of the doped regions is covered by an absorbing film and the doped regions are heated through the absorbing film, enabling an impurity region of the second conductivity type to be formed having two or more of the doped regions that have a same impurity concentration and differing carrier concentrations.

公开(公告)号：US09929194B2

公开(公告)日：2018-03-27

申请号：US15446775

申请日：2017-03-01

申请人： SK hynix Inc.

发明人： Yun-Hui Yang ,  Pyong-Su Kwag ,  Young-Jun Kwon ,  Min-Ki Na ,  Sung-Kun Park ,  Donghyun Woo ,  Cha-Young Lee ,  Ho-Ryeong Lee

IPC分类号： H01L31/102 ,  H01L27/146 ,  H01L29/04 ,  H01L29/16 ,  H01L29/51 ,  H01L29/78

CPC分类号： H01L27/14614 ,  H01L27/14609 ,  H01L27/1461 ,  H01L27/14616 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14689 ,  H01L29/04 ,  H01L29/16 ,  H01L29/511 ,  H01L29/7827

摘要： An image sensor includes a photoelectric conversion element including a first impurity region and a second impurity region, wherein the first impurity region contacts a first surface of a substrate, wherein the second impurity region has conductivity complementary to the first impurity region and is formed in the substrate and below the first impurity region; a pillar formed over the photoelectric conversion element; a transfer gate formed over the photoelectric conversion element to surround the pillar; and a channel layer formed between the transfer gate and the pillar and contacting the photoelectric conversion element, wherein the channel layer contacts the first impurity region and has the same conductivity as the second impurity region.

公开(公告)号：US09917089B2

公开(公告)日：2018-03-13

申请号：US15284759

申请日：2016-10-04

申请人： International Business Machines Corporation

发明人： Hemanth Jagannathan ,  Alexander Reznicek ,  Devendra K. Sadana ,  Charan V. Surisetty

IPC分类号： H01L29/76 ,  H01L27/092 ,  H01L29/20 ,  H01L29/267 ,  H01L29/165 ,  H01L29/08 ,  H01L29/10 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/78

CPC分类号： H01L27/0921 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/0262 ,  H01L21/302 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823892 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/20 ,  H01L29/267 ,  H01L29/66545 ,  H01L29/7848

摘要： A method for forming a semiconductor device comprises forming an insulator layer on a semiconductor substrate, removing portions of the insulator layer to form a first cavity and a second cavity, the first cavity exposing a first portion of the semiconductor substrate an the second cavity exposing a second portion of the semiconductor substrate, growing a first semiconductor material in the first cavity and the second cavity. Growing a second semiconductor material on the first semiconductor material in the first cavity and the second cavity, growing a third semiconductor material on the second semiconductor material in the first cavity and the second cavity. Forming a mask over the third semiconductor material in the first cavity, removing the third semiconductor material from the second cavity to expose the second semiconductor material in the second cavity, and growing a fourth semiconductor material on the second semiconductor material in the second cavity.

公开(公告)号：US09915961B2

公开(公告)日：2018-03-13

申请号：US14845885

申请日：2015-09-04

申请人： FUJI ELECTRIC CO., LTD.

发明人： Toshiyuki Matsui ,  Hitoshi Abe ,  Noriaki Yao

IPC分类号： G01K1/08 ,  G05F1/46 ,  H01L27/02 ,  G01K7/01 ,  H01L29/04 ,  H01L29/16 ,  H01L29/861

CPC分类号： G05F1/463 ,  G01K7/01 ,  H01L27/0255 ,  H01L29/04 ,  H01L29/16 ,  H01L29/861

摘要： A semiconductor device drive method achieves a balance between a lifetime and a detection sensitivity which are required for a temperature detection diode formed via an insulating film on a substrate on which an active element is formed. The semiconductor device drive method includes energizing the temperature detection diode with a constant current, the constant current having a current density value between an upper limit defined based on the lifetime of the temperature detection diode, and a lower defined based on a variation allowable voltage of an output voltage of the temperature detection diode with respect to a standard deviation.

公开(公告)号：US09911754B1

公开(公告)日：2018-03-06

申请号：US15288799

申请日：2016-10-07

申请人： MACRONIX International Co., Ltd.

发明人： Jung-Yi Guo ,  Chun-Min Cheng

IPC分类号： H01L27/115 ,  H01L27/11582 ,  H01L21/02 ,  H01L21/28 ,  H01L21/768 ,  H01L29/16 ,  H01L29/04 ,  H01L29/51

CPC分类号： H01L27/11582 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/0262 ,  H01L21/02667 ,  H01L21/76897 ,  H01L27/1157 ,  H01L29/04 ,  H01L29/16 ,  H01L29/513 ,  H01L29/518

摘要： A process for fabricating a 3D memory is shown. Linear stacks, each of which includes alternately stacked gate lines and insulating layers, are formed. A charge trapping layer is formed covering the linear stacks. An amorphous semiconductor layer is formed on the charge trapping layer. An ultra-thin cap layer is formed on the amorphous semiconductor layer. The amorphous semiconductor layer is annealed to form a crystalline channel layer, wherein agglomeration of the material of the amorphous semiconductor layer is suppressed by then ultra-thin cap layer.

公开(公告)号：US20180061982A1

公开(公告)日：2018-03-01

申请号：US15457799

申请日：2017-03-13

申请人： STMICROELECTRONICS S.R.L.

发明人： Marco Sambi ,  Fabrizio Fausto Renzo Toia ,  Marco Marchesi ,  Marco Morelli ,  Riccardo Depetro ,  Giuseppe Barillaro ,  Lucanos Marsilio Strambini

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L29/36 ,  H01L29/66 ,  H01L21/3063 ,  H01L21/265 ,  H01L21/308 ,  H01L21/02 ,  H01L29/08 ,  H01L21/762 ,  H03K17/687

CPC分类号： H01L29/7827 ,  H01L21/02233 ,  H01L21/02255 ,  H01L21/26513 ,  H01L21/3063 ,  H01L21/3081 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0665 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/32 ,  H01L29/36 ,  H01L29/41741 ,  H01L29/66128 ,  H01L29/66666 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/8611 ,  H03K17/687

摘要： An integrated electronic device having a semiconductor body including: a first electrode region having a first type of conductivity; and a second electrode region having a second type of conductivity, which forms a junction with the first electrode region. The integrated electronic device further includes a nanostructured semiconductor region, which extends in one of the first and second electrode regions.

公开(公告)号：US20180052196A1

公开(公告)日：2018-02-22

申请号：US15678616

申请日：2017-08-16

申请人： ATOMERA INCORPORATED

发明人： Richard Stephen ROY

IPC分类号： G01R31/28 ,  H01L29/15 ,  H01L27/092 ,  H01L29/78

CPC分类号： G01R31/2831 ,  G01R31/2644 ,  G01R31/2648 ,  G01R31/275 ,  G01R31/2894 ,  G01R31/31924 ,  G01R31/31932 ,  G11C11/4078 ,  G11C11/4087 ,  G11C29/50004 ,  H01L22/34 ,  H01L27/092 ,  H01L27/10897 ,  H01L29/105 ,  H01L29/152 ,  H01L29/16 ,  H01L29/7843 ,  H01L29/7849 ,  H03F3/45183 ,  H03F2200/453 ,  H03F2203/45361 ,  H03F2203/45368

摘要： A semiconductor device may include a substrate, active circuitry on the substrate and including differential transistor pairs, and threshold voltage test circuitry on the substrate. The threshold voltage test circuitry may include a pair of differential test transistors replicating the differential transistor pairs within the active circuitry, with each test transistor having a respective input and output, and at least one gain stage configured to amplify a difference between the outputs of the differential test transistors for measuring a threshold voltage thereof. The differential transistor pairs and the pair of differential test transistors may each include spaced apart source and drain regions, a channel region extending between the source and drain regions, and a gate overlying the channel region. Each of the channel regions may include a superlattice.

公开(公告)号：US09899272B2

公开(公告)日：2018-02-20

申请号：US15234170

申请日：2016-08-11

申请人： Samsung Electronics Co., Ltd.

发明人： Poren Tang ,  Sunjung Steve Kim ,  Moon Seung Yang ,  Seung Hun Lee ,  Hyun Jung Lee ,  Geun Hee Jeong

IPC分类号： H01L21/8238 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/10 ,  H01L29/06 ,  H01L27/092 ,  H01L21/8258

CPC分类号： H01L21/823892 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02458 ,  H01L21/02463 ,  H01L21/02499 ,  H01L21/02532 ,  H01L21/0254 ,  H01L21/02546 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/308 ,  H01L21/823807 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/78

摘要： Methods of fabricating semiconductor device are provided including forming first and second material layers for a first transistor using epitaxial growth processes. A recess region is formed by partially etching the first and second material layers. Third and fourth material layers for a second transistor are formed using epitaxial growth processes.

公开(公告)号：US20180040716A1

公开(公告)日：2018-02-08

申请号：US15492343

申请日：2017-04-20

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Kangguo Cheng ,  Juntao Li

IPC分类号： H01L29/66 ,  H01L21/311 ,  H01L29/04 ,  H01L29/08 ,  H01L29/78 ,  H01L21/02

CPC分类号： H01L29/66666 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/32105 ,  H01L21/477 ,  H01L27/0886 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/49 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/93

摘要： A method of forming a vertical fin field effect transistor having a consistent channel width, including forming one or more vertical fin(s) on the substrate, wherein the one or more vertical fin(s) have a tapered profile, oxidizing the one or more vertical fin(s) to form an oxide by consuming at least a portion of the vertical fin material, and removing the oxide from the one or more vertical fin(s), wherein the one or more vertical fin(s) include a tapered upper portion, a tapered lower portion and a straight channel portion there between.