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    Forming dual metallization interconnect structures in single metallization level
    1.
    发明授权
    Forming dual metallization interconnect structures in single metallization level 有权

    公开(公告)号：US10559530B2

    公开(公告)日：2020-02-11

    申请号：US15855133

    申请日：2017-12-27

    申请人： International Business Machines Corporation

    发明人： Hari P. Amanapu ,  Charan V. Surisetty ,  Raghuveer R. Patlolla

    IPC分类号： H01L21/768 ,  H01L23/528 ,  H01L23/532

    摘要： Techniques are provided to fabricate metallic interconnect structures in a single metallization level, wherein different width metallic interconnect structures are formed of different metallic materials to eliminate or minimize void formation in the metallic interconnect structures. For example, a semiconductor device includes an insulating layer disposed on a substrate, and a first metallic line and a second metallic line formed in the insulating layer. The first metallic line has a first width, and the second metallic line has a second width which is greater than the first width. The first metallic line is formed of a first metallic material, and the second metallic line is formed of a second metallic material, which is different from the first metallic material. For example, the first metallic material is cobalt or ruthenium, and the second metallic material is copper.

    FORMING DUAL METALLIZATION INTERCONNECT STRUCTURES IN SINGLE METALLIZATION LEVEL
    2.
    发明申请
    FORMING DUAL METALLIZATION INTERCONNECT STRUCTURES IN SINGLE METALLIZATION LEVEL 审中-公开

    公开(公告)号：US20190311986A1

    公开(公告)日：2019-10-10

    申请号：US16445428

    申请日：2019-06-19

    申请人： International Business Machines Corporation

    发明人： Hari P. Amanapu ,  Charan V. Surisetty ,  Raghuveer R. Patlolla

    IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L23/532

    摘要： Techniques are provided to fabricate metallic interconnect structures in a single metallization level, wherein different width metallic interconnect structures are formed of different metallic materials to eliminate or minimize void formation in the metallic interconnect structures. For example, a semiconductor device includes an insulating layer disposed on a substrate, and a first metallic line and a second metallic line formed in the insulating layer. The first metallic line has a first width, and the second metallic line has a second width which is greater than the first width. The first metallic line is formed of a first metallic material, and the second metallic line is formed of a second metallic material, which is different from the first metallic material. For example, the first metallic material is cobalt or ruthenium, and the second metallic material is copper.

    Growing buffer layers in bulk finFET structures
    6.
    发明授权
    Growing buffer layers in bulk finFET structures 有权
    体积finFET结构中生长的缓冲层

    公开(公告)号：US09159811B2

    公开(公告)日：2015-10-13

    申请号：US14109989

    申请日：2013-12-18

    申请人： International Business Machines Corporation

    发明人： Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Charan V. Surisetty

    IPC分类号： H01L21/8242 ,  H01L29/66 ,  H01L21/8234

    CPC分类号： H01L21/823431 ,  H01L29/66795 ,  H01L29/7848

    摘要： A semiconductor structure may be formed by forming a fin on a substrate, forming a gate over a portion of the fin, removing a portion of the fin not below the gate to expose a sidewall of the fin beneath the gate and a top surface of the substrate, forming a first protective layer on the top surface of the substrate but not on the sidewall of the fin, forming a second protective layer on the sidewall of the fin prevented from forming on the top surface of the substrate by the first protective layer, removing the first protective layer to expose the top surface of the substrate, forming a buffer layer on the top surface of the substrate; the buffer layer prevented from forming on the sidewall of the fin by the second protective layer, and forming a source-drain region on the buffer layer electrically connected to the fin.

    摘要翻译： 半导体结构可以通过在衬底上形成翅片而形成翅片，在翅片的一部分上形成栅极，去除不在栅极下面的鳍片的一部分以暴露栅极下方的翅片的侧壁和 衬底，在衬底的顶表面上形成第一保护层，而不在鳍的侧壁上，在翅片的侧壁上形成第二保护层，防止由第一保护层在衬底的顶表面上形成， 去除第一保护层以暴露衬底的顶表面，在衬底的顶表面上形成缓冲层; 缓冲层通过第二保护层防止在翅片的侧壁上形成，并且在与鳍片电连接的缓冲层上形成源极 - 漏极区域。

    EMBEDDED INTERLEVEL DIELECTRIC BARRIER LAYERS FOR REPLACEMENT METAL GATE FIELD EFFECT TRANSISTORS
    7.
    发明申请
    EMBEDDED INTERLEVEL DIELECTRIC BARRIER LAYERS FOR REPLACEMENT METAL GATE FIELD EFFECT TRANSISTORS 有权
    用于替换金属栅极场效应晶体管的嵌入式交互介质屏障层

    公开(公告)号：US20150108589A1

    公开(公告)日：2015-04-23

    申请号：US14059480

    申请日：2013-10-22

    申请人： International Business Machines Corporation

    发明人： Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Charan V. Surisetty

    IPC分类号： H01L29/51 ,  H01L21/283 ,  H01L29/423 ,  H01L21/28

    CPC分类号： H01L29/511 ,  H01L21/28008 ,  H01L21/283 ,  H01L21/76829 ,  H01L21/76897 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66628

    摘要： A semiconductor structure may be formed by forming a sacrificial gate above a substrate covered by a hard mask, depositing a first interlevel dielectric (ILD) layer above the sacrificial gate, recessing the first ILD layer to a thickness less than the height of the sacrificial gate, depositing an etch barrier layer above the first ILD layer, depositing a second ILD layer above the etch barrier layer, planarizing the second ILD layer and the etch barrier layer to expose the hard mask using the hard mask as a planarization stop, removing the hard mask and sacrificial gate to form a gate cavity, forming a replacement metal gate in the gate cavity, removing the second ILD layer, and planarizing the replacement metal gate using the etch barrier layer as a planarization stop. A supplementary electrode layer may be formed above the replacement metal gate prior to planarizing the replacement metal gate.

    摘要翻译： 可以通过在由硬掩模覆盖的衬底上方形成牺牲栅极来形成半导体结构，在牺牲栅极上方沉积第一层间电介质（ILD）层，使第一ILD层凹陷到小于牺牲栅极的高度的厚度 在第一ILD层之上沉积蚀刻阻挡层，在蚀刻阻挡层上方沉积第二ILD层，使第二ILD层和蚀刻阻挡层平坦化，以使用硬掩模露出硬掩模作为平坦化停止，去除硬的 掩模和牺牲栅极以形成栅极腔，在栅极腔中形成替代金属栅极，去除第二ILD层，以及使用蚀刻阻挡层作为平坦化停止来平坦化替换金属栅极。 辅助电极层可以在替换金属栅极平坦化之前形成在替换金属栅极之上。