公开(公告)号：US20140264837A1

公开(公告)日：2014-09-18

申请号：US13870674

申请日：2013-04-25

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Hsien-Wei Chen ,  Tsung-Yuan Yu ,  Hao-Yi Tsai ,  Mirng-Ji Lii ,  Chen-Hua Yu

IPC分类号： H01L23/498 ,  H01L23/00

CPC分类号： H01L24/11 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/49811 ,  H01L23/525 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/83 ,  H01L24/94 ,  H01L2224/02235 ,  H01L2224/02351 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/03013 ,  H01L2224/03019 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05569 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/1191 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/8385 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/00

摘要： A semiconductor device, including a protective layer overlying a contact pad and a dummy pad on a semiconductor substrate, an interconnect structure overlying the protective layer and contacting part of the dummy pad through a contact via passing through the protective layer, a bump overlying the interconnect structure positioned over the dummy pad.

摘要翻译： 一种半导体器件，包括覆盖接触焊盘的保护层和半导体衬底上的虚拟焊盘，覆盖保护层并通过穿过保护层的接触部分接触虚拟焊盘的一部分的互连结构，覆盖互连 结构位于虚拟垫上。

公开(公告)号：US20140264735A1

公开(公告)日：2014-09-18

申请号：US14182116

申请日：2014-02-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hao-Yi Tsai ,  Hsien-Wei Chen ,  Hung-Yi Kuo ,  Tsung-Yuan Yu

IPC分类号： H01L49/02 ,  H01L23/522

CPC分类号： H01L23/5227 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/585 ,  H01L27/0688 ,  H01L27/08 ,  H01L28/10 ,  H01L29/0619 ,  H01L2924/0002 ,  H01L2924/00

摘要： A system and method for providing and manufacturing an inductor is provided. In an embodiment similar masks are reutilized to form differently sized inductors. For example, a two turn inductor and a three turn inductor may share masks for interconnects and coils, while only masks necessary for connections between the interconnects and coils may need to be newly developed.

摘要翻译： 提供了一种用于提供和制造电感器的系统和方法。 在一个实施例中，类似的掩模被重新利用以形成不同尺寸的电感器。 例如，两转电感器和三转电感器可以共享用于互连和线圈的掩模，而仅需要新开发互连和线圈之间的连接所需的掩模。

公开(公告)号：US08722529B2

公开(公告)日：2014-05-13

申请号：US14058862

申请日：2013-10-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsien-Wei Chen ,  Yu-Wen Liu ,  Hao-Yi Tsai ,  Shin-Puu Jeng ,  Ying-Ju Chen

IPC分类号： H01L21/44

CPC分类号： H01L24/03 ,  H01L23/3192 ,  H01L23/585 ,  H01L24/05 ,  H01L24/08 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/02126 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05093 ,  H01L2224/05094 ,  H01L2224/05095 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48684 ,  H01L2224/48724 ,  H01L2224/48739 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48784 ,  H01L2224/85 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/48744

摘要： An integrated circuit structure includes a bond pad; an Mtop pad located directly underlying the bond pad; an Mtop-1 pad having at least a portion directly underlying the Mtop pad, wherein at least one of the Mtop pad and the Mtop-1 pad has a horizontal dimension smaller than a horizontal dimension of the bond pad; a plurality of vias interconnecting the Mtop pad and the Mtop-1 pad; and a bond ball on the bond pad. Each of the Mtop pad and the Mtop-1 pad has positive enclosures to the bond ball in all horizontal directions.

摘要翻译： 集成电路结构包括接合焊盘; 直接位于接合垫下面的Mtop垫; Mtop-1垫具有直接位于Mtop垫下方的至少一部分，其中Mtop垫和Mtop-1垫中的至少一个具有小于接合垫的水平尺寸的水平尺寸; 将Mtop焊盘和Mtop-1焊盘互连的多个通孔; 和粘结垫上的粘结球。 每个Mtop垫和Mtop-1垫在所有水平方向上都具有粘结球的正面外壳。

公开(公告)号：US12068212B2

公开(公告)日：2024-08-20

申请号：US17718309

申请日：2022-04-11

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Hsuan Tai ,  Chih-Hua Chen ,  Hao-Yi Tsai ,  Yu-Chih Huang ,  Chia-Hung Liu ,  Ting-Ting Kuo

IPC分类号： H01L23/31 ,  H01L21/56 ,  H01L21/66 ,  H01L21/683 ,  H01L21/78 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532 ,  H01L23/538 ,  H01L25/00 ,  H01L25/10 ,  H01L25/065

CPC分类号： H01L23/3114 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L22/20 ,  H01L22/32 ,  H01L23/3128 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/82 ,  H01L24/92 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/83005 ,  H01L2224/83101 ,  H01L2224/92244 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/06596 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/2919 ,  H01L2924/00014 ,  H01L2224/83101 ,  H01L2924/00014

摘要： A package structure and a method of manufacturing the same are provided. The package structure includes a die, an encapsulant, a first redistribution line (RDL) structure, a second RDL structure, a conductive terminal, and a through via. The encapsulant laterally encapsulates the die. The first redistribution line (RDL) structure on a first side of the die and the encapsulant, wherein the first RDL structure comprises a dielectric layer and a redistribution layer in the dielectric layer. The second RDL structure is located on a second side of the die and the encapsulant. The conductive terminal is connected to the redistribution layer. The through via extends through the encapsulant and the redistribution layer to contact the conductive terminal and the second RDL structure.

公开(公告)号：US12015017B2

公开(公告)日：2024-06-18

申请号：US17321528

申请日：2021-05-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Hsuan Tai ,  Hao-Yi Tsai ,  Yu-Chih Huang ,  Chia-Hung Liu ,  Ting-Ting Kuo ,  Ban-Li Wu ,  Ying-Cheng Tseng ,  Chi-Hui Lai

IPC分类号： H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L23/00

CPC分类号： H01L25/105 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L25/50 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2225/1058

摘要： A package structure including a first redistribution layer, a semiconductor die, through insulator vias, an insulating encapsulant and a second redistribution layer. The first redistribution layer includes a dielectric layer, a conductive layer, and connecting portions electrically connected to the conductive layer. The dielectric layer has first and second surfaces, the connecting portions has a first side, a second side, and sidewalls joining the first side to the second side. The first side of the connecting portions is exposed from and coplanar with the first surface of the dielectric layer. The semiconductor die is disposed on the second surface of the dielectric layer. The through insulator vias are connected to the conductive layer. The insulating encapsulant is disposed on the dielectric layer and encapsulating the semiconductor die and the through insulator vias. The second redistribution layer is disposed on the semiconductor die and over the insulating encapsulant.

公开(公告)号：US20240194591A1

公开(公告)日：2024-06-13

申请号：US18582494

申请日：2024-02-20

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Hsuan Tai ,  Hao-Yi Tsai ,  Tsung-Hsien Chiang ,  Yu-Chih Huang ,  Chia-Hung Liu ,  Ban-Li Wu ,  Ying-Cheng Tseng ,  Po-Chun Lin

IPC分类号： H01L23/522 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/48 ,  H01L23/528

CPC分类号： H01L23/5226 ,  H01L21/56 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/5283 ,  H01L24/09 ,  H01L24/17 ,  H01L24/33 ,  H01L24/73 ,  H01L2224/0231 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/73204

摘要： A package structure includes a thermal dissipation structure including a substrate, a first encapsulant laterally covering the substrate, a die disposed on the substrate and including a sensing region, a second encapsulant laterally covering the die, and a redistribution structure disposed on the die and the second encapsulant. An outer sidewall of the second encapsulant is laterally offset from an outer sidewall of the first encapsulant. The die is electrically coupled to the substrate through the redistribution structure, and the redistribution structure includes a hollow region overlying the sensing region of the die.

公开(公告)号：US20240178120A1

公开(公告)日：2024-05-30

申请号：US18166450

申请日：2023-02-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chung-Ming Weng ,  Tzu-Sung Huang ,  Wei-Kang Hsieh ,  Hao-Yi Tsai ,  Ming-Hung Tseng ,  Tsung-Hsien Chiang ,  Yen-Liang Lin ,  Chu-Chun Chueh

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/544 ,  H01L25/16

CPC分类号： H01L23/49838 ,  H01L21/4857 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/544 ,  H01L24/24 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L25/16 ,  H01L23/49822 ,  H01L2223/54433 ,  H01L2224/24227 ,  H01L2224/244 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/82106 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/92244 ,  H01L2924/19106

摘要： An integrated fan-out package includes a first redistribution structure, a die, conductive structures, an encapsulant, and a second redistribution structure. The first redistribution structure has first regions and a second region surrounding the first regions. A metal density in the first regions is smaller than a metal density in the second region. The die is disposed over the first redistribution structure. The conductive structures are disposed on the first redistribution structure to surround the die. Vertical projections of the conductive structures onto the first redistribution structure fall within the first regions of the first redistribution structure. The encapsulant encapsulates the die and the conductive structures. The second redistribution structure is disposed on the encapsulant, the die, and the conductive structures.

公开(公告)号：US20240162171A1

公开(公告)日：2024-05-16

申请号：US18418318

申请日：2024-01-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Wei Chen ,  Tzuan-Horng Liu ,  Chia-Hung Liu ,  Hao-Yi Tsai

IPC分类号： H01L23/60 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

CPC分类号： H01L23/60 ,  H01L21/568 ,  H01L23/3135 ,  H01L24/32 ,  H01L24/83 ,  H01L25/0657 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/32145

摘要： A device die including a first semiconductor die, a second semiconductor die, an anti-arcing layer and a first insulating encapsulant is provided. The second semiconductor die is stacked over and electrically connected to the first semiconductor die. The anti-arcing layer is in contact with the second semiconductor die. The first insulating encapsulant is disposed over the first semiconductor die and laterally encapsulates the second semiconductor die. Furthermore, methods for fabricating device dies are provided.

公开(公告)号：US11929318B2

公开(公告)日：2024-03-12

申请号：US17315365

申请日：2021-05-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Hsuan Tai ,  Hao-Yi Tsai ,  Tsung-Hsien Chiang ,  Yu-Chih Huang ,  Chia-Hung Liu ,  Ban-Li Wu ,  Ying-Cheng Tseng ,  Po-Chun Lin

IPC分类号： H01L23/34 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L23/5226 ,  H01L21/56 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/5283 ,  H01L24/09 ,  H01L24/17 ,  H01L24/33 ,  H01L24/73 ,  H01L2224/0231 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/73204

摘要： A package structure includes a thermal dissipation structure, a first encapsulant, a die, a through integrated fan-out via (TIV), a second encapsulant, and a redistribution layer (RDL) structure. The thermal dissipation structure includes a substrate and a first conductive pad disposed over the substrate. The first encapsulant laterally encapsulates the thermal dissipation structure. The die is disposed on the thermal dissipation structure. The TIV lands on the first conductive pad of the thermal dissipation structure and is laterally aside the die. The second encapsulant laterally encapsulates the die and the TIV. The RDL structure is disposed on the die and the second encapsulant.

公开(公告)号：US20240063075A1

公开(公告)日：2024-02-22

申请号：US17890210

申请日：2022-08-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Pavithra Sriram ,  Kuo-Lung Pan ,  Po-Yuan Teng ,  Cheng-Chieh Wu ,  Mao-Yen Chang ,  Yu-Chia Lai ,  Shu-Rong Chun ,  Hao-Yi Tsai

IPC分类号： H01L23/367 ,  H01L25/065 ,  H01L25/10 ,  H01L21/56 ,  H01L23/31

CPC分类号： H01L23/367 ,  H01L25/0655 ,  H01L25/105 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3135 ,  H01L24/16

摘要： A semiconductor device includes a first redistribution structure, a first semiconductor package, a second semiconductor package, an encapsulation layer, a first thermal interface material (TIM) layer, and a second TIM layer. The first semiconductor package and the second semiconductor package are respectively disposed on the first redistribution structure and laterally disposed aside with each other. The encapsulation layer encapsulates and surrounds the first semiconductor package and the second semiconductor package. The first semiconductor package and the second semiconductor package are respectively exposed from the encapsulation layer. The first TIM layer and the second TIM layer are respectively disposed on back surfaces of the first semiconductor package and the second semiconductor package. A top surface of the first TIM layer and a top surface of the second TIM layer are coplanar with a top surface of the encapsulation layer.