公开(公告)号：US20240234375A1

公开(公告)日：2024-07-11

申请号：US18429471

申请日：2024-02-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hao-Yi Tsai ,  Cheng-Chieh Hsieh ,  Tsung-Hsien Chiang ,  Hui-Chun Chiang ,  Tzu-Sung Huang ,  Ming-Hung Tseng ,  Kris Lipu Chuang ,  Chung-Ming Weng ,  Tsung-Yuan Yu ,  Tzuan-Horng Liu

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/10

CPC classification number: H01L25/0657 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L25/105 ,  H01L25/50 ,  H01L24/06 ,  H01L24/73 ,  H01L2224/02141 ,  H01L2224/0311 ,  H01L2224/0312 ,  H01L2224/05559 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/06135 ,  H01L2224/08225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2225/1035 ,  H01L2225/1058

Abstract: A semiconductor package including a first semiconductor die, a second semiconductor die, a first insulating encapsulation, a dielectric layer structure, a conductor structure and a second insulating encapsulation is provided. The first semiconductor die includes a first semiconductor substrate and a through substrate via (TSV) extending from a first side to a second side of the semiconductor substrate. The second semiconductor die is disposed on the first side of the semiconductor substrate. The first insulating encapsulation on the second semiconductor die encapsulates the first semiconductor die. A terminal of the TSV is coplanar with a surface of the first insulating encapsulation. The dielectric layer structure covers the first semiconductor die and the first insulating encapsulation. The conductor structure extends through the dielectric layer structure and contacts with the through substrate via. The second insulating encapsulation contacts with the second semiconductor die, the first insulting encapsulation, and the dielectric layer structure.

公开(公告)号：US11935871B2

公开(公告)日：2024-03-19

申请号：US17460340

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hao-Yi Tsai ,  Cheng-Chieh Hsieh ,  Tsung-Hsien Chiang ,  Hui-Chun Chiang ,  Tzu-Sung Huang ,  Ming-Hung Tseng ,  Kris Lipu Chuang ,  Chung-Ming Weng ,  Tsung-Yuan Yu ,  Tzuan-Horng Liu

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/10

CPC classification number: H01L25/0657 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L25/105 ,  H01L25/50 ,  H01L24/06 ,  H01L24/73 ,  H01L2224/02141 ,  H01L2224/0311 ,  H01L2224/0312 ,  H01L2224/05559 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/06135 ,  H01L2224/08225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2225/1035 ,  H01L2225/1058

Abstract: A semiconductor package including a first semiconductor die, a second semiconductor die, a first insulating encapsulation, a dielectric layer structure, a conductor structure and a second insulating encapsulation is provided. The first semiconductor die includes a first semiconductor substrate and a through silicon via (TSV) extending from a first side to a second side of the semiconductor substrate. The second semiconductor die is disposed on the first side of the semiconductor substrate. The first insulating encapsulation on the second semiconductor die encapsulates the first semiconductor die. A terminal of the TSV is coplanar with a surface of the first insulating encapsulation. The dielectric layer structure covers the first semiconductor die and the first insulating encapsulation. The conductor structure extends through the dielectric layer structure and contacts with the through silicon via. The second insulating encapsulation contacts with the second semiconductor die, the first insulting encapsulation, and the dielectric layer structure.

公开(公告)号：US20230369263A1

公开(公告)日：2023-11-16

申请号：US17741463

申请日：2022-05-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kris Lipu Chuang ,  Hsiu-Jen Lin ,  Tzu-Sung Huang ,  Hsin-Yu Pan

IPC: H01L23/00 ,  H01L25/10 ,  H01L23/31 ,  H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L24/06 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/20 ,  H01L25/105 ,  H01L2221/68359 ,  H01L2224/06519 ,  H01L2224/214 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1094

Abstract: A semiconductor package includes a substrate, a redistribution circuit layer, and a protective layer. The redistribution circuit layer is over the substrate and includes a plurality of functional pads electrically connected to the substrate, and a dummy pad pattern electrically disconnected from the plurality of functional pads, wherein the dummy pad pattern includes a plurality of pad portions connected to one another. The protective layer is disposed over the redistribution circuit layer and comprising a plurality of first openings spaced apart from one another and respectively revealing the plurality of pad portions.

公开(公告)号：US11502039B2

公开(公告)日：2022-11-15

申请号：US17026898

申请日：2020-09-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tzu-Sung Huang ,  Hsiu-Jen Lin ,  Hao-Yi Tsai ,  Ming Hung Tseng ,  Tsung-Hsien Chiang ,  Tin-Hao Kuo ,  Yen-Liang Lin

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L21/768

Abstract: In an embodiment, a device includes: a back-side redistribution structure including: a metallization pattern on a first dielectric layer; and a second dielectric layer on the metallization pattern; a through via extending through the first dielectric layer to contact the metallization pattern; an integrated circuit die adjacent the through via on the first dielectric layer; a molding compound on the first dielectric layer, the molding compound encapsulating the through via and the integrated circuit die; a conductive connector extending through the second dielectric layer to contact the metallization pattern, the conductive connector being electrically connected to the through via; and an intermetallic compound at the interface of the conductive connector and the metallization pattern, the intermetallic compound extending only partially into the metallization pattern.

公开(公告)号：US10950519B2

公开(公告)日：2021-03-16

申请号：US16427569

申请日：2019-05-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tzu-Sung Huang ,  Ming Hung Tseng ,  Yen-Liang Lin ,  Hao-Yi Tsai ,  Chi-Ming Tsai ,  Chung-Shi Liu ,  Chih-Wei Lin ,  Ming-Che Ho

IPC: H01L23/31 ,  H01L23/16 ,  H01L23/522 ,  H01L23/528 ,  H01L21/56 ,  H01L21/768

Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.

公开(公告)号：US10790244B2

公开(公告)日：2020-09-29

申请号：US15881362

申请日：2018-01-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tzu-Sung Huang ,  Chen-Hua Yu ,  Hung-Yi Kuo ,  Hao-Yi Tsai ,  Ming Hung Tseng

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/64 ,  H01L23/485 ,  H01L23/552 ,  H01L49/02 ,  H01L21/683 ,  H01L23/31

Abstract: In an embodiment, a device includes: a conductive shield on a first dielectric layer; a second dielectric layer on the first dielectric layer and the conductive shield, the first and second dielectric layers surrounding the conductive shield, the second dielectric layer including: a first portion disposed along an outer periphery of the conductive shield; a second portion extending through a center region of the conductive shield; and a third portion extending through a channel region of the conductive shield, the third portion connecting the first portion to the second portion; a coil on the second dielectric layer, the coil disposed over the conductive shield; an integrated circuit die on the second dielectric layer, the integrated circuit die disposed outside of the coil; and an encapsulant surrounding the coil and the integrated circuit die, top surfaces of the encapsulant, the integrated circuit die, and the coil being level.

公开(公告)号：US20190148301A1

公开(公告)日：2019-05-16

申请号：US15907869

申请日：2018-02-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tzu-Sung Huang ,  Hsiu-Jen Lin ,  Hao-Yi Tsai ,  Ming Hung Tseng ,  Tsung-Hsien Chiang ,  Tin-Hao Kuo ,  Yen-Liang Lin

IPC: H01L23/538 ,  H01L23/498 ,  H01L21/768

Abstract: In an embodiment, a device includes: a back-side redistribution structure including: a metallization pattern on a first dielectric layer; and a second dielectric layer on the metallization pattern; a through via extending through the first dielectric layer to contact the metallization pattern; an integrated circuit die adjacent the through via on the first dielectric layer; a molding compound on the first dielectric layer, the molding compound encapsulating the through via and the integrated circuit die; a conductive connector extending through the second dielectric layer to contact the metallization pattern, the conductive connector being electrically connected to the through via; and an intermetallic compound at the interface of the conductive connector and the metallization pattern, the intermetallic compound extending only partially into the metallization pattern.

公开(公告)号：US20230275030A1

公开(公告)日：2023-08-31

申请号：US18303543

申请日：2023-04-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tzu-Sung Huang ,  Cheng-Chieh Hsieh ,  Hsiu-Jen Lin ,  Hui-Jung Tsai ,  Hung-Yi Kuo ,  Hao-Yi Tsai ,  Ming-Hung Tseng ,  Yen-Liang Lin ,  Chun-Ti Lu ,  Chung-Ming Weng

IPC: H01L23/538 ,  H01L23/31 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00

CPC classification number: H01L23/5389 ,  H01L23/3121 ,  H01L25/0657 ,  H01L25/50 ,  H01L21/56 ,  H01L21/78 ,  H01L24/94

Abstract: A package structure including a first semiconductor die, a second semiconductor die, first conductive pillars and a first insulating encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure and a first redistribution circuit structure. The semiconductor substrate includes a first portion and a second portion disposed on the first portion. The interconnect structure is disposed on the second portion, the first redistribution circuit structure is disposed on the interconnect structure, and the lateral dimension of the first portion is greater than the lateral dimension of the second portion. The second semiconductor die is disposed on the first semiconductor die. The first conductive pillars are disposed on the first redistribution circuit structure of the first semiconductor die. The first insulating encapsulation is disposed on the first portion. The first insulating encapsulation laterally encapsulates the second semiconductor die, the first conductive pillars and the second portion.

公开(公告)号：US11664325B2

公开(公告)日：2023-05-30

申请号：US17666579

申请日：2022-02-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tzu-Sung Huang ,  Cheng-Chieh Hsieh ,  Hsiu-Jen Lin ,  Hui-Jung Tsai ,  Hung-Yi Kuo ,  Hao-Yi Tsai ,  Ming-Hung Tseng ,  Yen-Liang Lin ,  Chun-Ti Lu ,  Chung-Ming Weng

IPC: H01L21/56 ,  H01L23/538 ,  H01L23/31 ,  H01L25/065 ,  H01L25/00 ,  H01L21/78 ,  H01L23/00

CPC classification number: H01L23/5389 ,  H01L21/56 ,  H01L21/78 ,  H01L23/3121 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50

Abstract: A package structure including a first semiconductor die, a second semiconductor die, first conductive pillars and a first insulating encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure and a first redistribution circuit structure. The semiconductor substrate includes a first portion and a second portion disposed on the first portion.
The interconnect structure is disposed on the second portion, the first redistribution circuit structure is disposed on the interconnect structure, and the lateral dimension of the first portion is greater than the lateral dimension of the second portion. The second semiconductor die is disposed on the first semiconductor die. The first conductive pillars are disposed on the first redistribution circuit structure of the first semiconductor die. The first insulating encapsulation is disposed on the first portion. The first insulating encapsulation laterally encapsulates the second semiconductor die, the first conductive pillars and the second portion.

公开(公告)号：US20230116861A1

公开(公告)日：2023-04-13

申请号：US18065199

申请日：2022-12-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tzu-Sung Huang ,  Chen-Hua Yu ,  Hao-Yi Tsai ,  Hung-Yi KUO ,  Ming Hung Tseng

IPC: H01F27/28 ,  H02J50/80 ,  H02J50/10 ,  H01F38/14 ,  H01F41/04 ,  H01F41/10

Abstract: Coil structures and methods of forming are provided. The coil structure includes a substrate. A plurality of coils is disposed over the substrate, each coil comprising a conductive element that forms a continuous spiral having a hexagonal shape in a plan view of the coil structure. The plurality of coils is arranged in a honeycomb pattern, and each conductive element is electrically connected to an external electrical circuit.