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公开(公告)号：US09799394B2
公开(公告)日：2017-10-24
申请号：US14696795
申请日：2015-04-27
Inventor： Wei-Cheng Wu , Kao-Cheng Lin , Wei Min Chan , Yen-Huei Chen
IPC: G11C11/419
CPC classification number: G11C11/419
Abstract: A static random access memory (SRAM) including at least a memory cell array, a first data line, a second data line, a third data line and a driver circuit. The first data line is electrically coupled with the memory cell array. The second data line is electrically coupled with the memory cell array. The driver circuit is electrically coupled with the first data line, the second data line and the third data line. The driver circuit includes a recovery circuit electrically coupled with the first data line, the second data line and the third data line. During a write operation of the SRAM, the recovery circuit is configured to pull a voltage level of the first data line to a first voltage level when the recovery circuit is enabled.
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公开(公告)号：US09760670B2
公开(公告)日：2017-09-12
申请号：US15174795
申请日：2016-06-06
Inventor： Tzu-Yu Wang , Wei-Cheng Wu , Kuo-Ching Hsu , Shang-Yun Hou , Shin-Puu Jeng
CPC classification number: G06F17/5077 , G06F17/5009 , G06F17/5081 , G06F2217/02 , G06F2217/06 , G06F2217/08 , G06F2217/38 , G06F2217/40 , H01L24/11 , H01L24/13 , H01L2224/13005 , H01L2224/16227 , H01L2924/15311
Abstract: Semiconductor device design methods and conductive bump pattern enhancement methods are disclosed. In some embodiments, a method of designing a semiconductor device includes designing a conductive bump pattern design, and implementing a conductive bump pattern enhancement algorithm on the conductive bump pattern design to create an enhanced conductive bump pattern design. A routing pattern is designed based on the enhanced conductive bump pattern design. A design rule checking (DRC) procedure is performed on the routing pattern.
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公开(公告)号：US09741690B1
公开(公告)日：2017-08-22
申请号：US15261202
申请日：2016-09-09
Inventor： Cheng-Hsien Hsieh , Li-Han Hsu , Wei-Cheng Wu , Hsien-Wei Chen , Der-Chyang Yeh , Chi-Hsi Wu , Chen-Hua Yu
IPC: H01L23/48 , H01L23/52 , H01L29/40 , H01L25/065 , H01L23/31 , H01L23/538 , H01L21/56 , H01L21/768 , H01L25/00
CPC classification number: H01L25/0655 , H01L21/56 , H01L21/561 , H01L21/568 , H01L21/76895 , H01L23/3107 , H01L23/3128 , H01L23/481 , H01L23/49811 , H01L23/5384 , H01L23/5385 , H01L23/5386 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L25/0652 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/04105 , H01L2224/12105 , H01L2224/19 , H01L2224/24137 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73267 , H01L2224/92244 , H01L2224/97 , H01L2225/0651 , H01L2225/0652 , H01L2225/06548 , H01L2225/06568 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/15311 , H01L2924/3512 , H01L2224/83 , H01L2224/83005 , H01L2924/00014
Abstract: An embodiment package includes a first integrated circuit die, an encapsulent around the first integrated circuit die, and a conductive line electrically connecting a first conductive via to a second conductive via. The conductive line includes a first segment over the first integrated circuit die and having a first lengthwise dimension extending in a first direction and a second segment having a second lengthwise dimension extending in a second direction different than the first direction. The second segment extends over a boundary between the first integrated circuit die and the encapsulant.
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公开(公告)号：US09704565B2
公开(公告)日：2017-07-11
申请号：US15012970
申请日：2016-02-02
Inventor： Wei-Cheng Wu , Wei Min Chan , Yen-Huei Chen , Hung-Jen Liao , Ping-Wei Wang
IPC: G11C11/40 , G11C11/419 , G11C11/4063 , G11C11/409 , G11C11/412
CPC classification number: G11C11/419 , G11C11/4063 , G11C11/409 , G11C11/412
Abstract: A method of using a static random access memory (SRAM) includes pre-discharging a data line to a reference voltage, activating a bit cell connected to the data line, wherein the bit cell comprises a p-type pass gate, and exchanging bit information between the data line and the activated bit cell.
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公开(公告)号：US20170178983A1
公开(公告)日：2017-06-22
申请号：US15449683
申请日：2017-03-03
Inventor： Tzuan-Horng Liu , Chen-Hua Yu , Hsien-Pin Hu , Tzu-Yu Wang , Wei-Cheng Wu , Shang-Yun Hou , Shin-Puu Jeng
IPC: H01L21/66 , G01R1/073 , H01L21/48 , H01L23/498 , H01L23/58
CPC classification number: H01L22/32 , G01R1/07378 , H01L21/4853 , H01L21/486 , H01L21/561 , H01L21/6835 , H01L22/30 , H01L22/34 , H01L23/49811 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/5226 , H01L23/585 , H01L2221/68331 , H01L2224/05001 , H01L2224/05026 , H01L2224/05572 , H01L2224/056 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2224/81192 , H01L2224/81815 , H01L2224/97 , H01L2924/01322 , H01L2924/15311 , H01L2924/00014 , H01L2224/81 , H01L2924/00 , H01L2224/05124 , H01L2224/05147
Abstract: An embodiment of the disclosure is a structure comprising an interposer. The interposer has a test structure extending along a periphery of the interposer, and at least a portion of the test structure is in a first redistribution element. The first redistribution element is on a first surface of a substrate of the interposer. The test structure is intermediate and electrically coupled to at least two probe pads.
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Patent Agency Ranking
公开(公告)号：US20170084529A1
公开(公告)日：2017-03-23
申请号：US15357205
申请日：2016-11-21
Inventor： Cheng-Hsien Hsieh , Hsien-Wei Chen , Chi-Hsi Wu , Chen-Hua Yu , Der-Chyang Yeh , Li-Han Hsu , Wei-Cheng Wu
IPC: H01L23/498 , H01L23/31
CPC classification number: H01L23/49838 , H01L23/3171 , H01L23/3192 , H01L23/498 , H01L23/49827 , H01L23/522 , H01L23/528 , H01L23/5329 , H01L23/585 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/05572 , H01L2224/05666 , H01L2224/05681 , H01L2224/11849 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/94 , H01L2924/10252 , H01L2924/10253 , H01L2924/10271 , H01L2924/1032 , H01L2924/10336 , H01L2924/10337 , H01L2924/10338 , H01L2924/10339 , H01L2924/10342 , H01L2924/10351 , H01L2924/14 , H01L2924/3512 , H01L2924/014 , H01L2924/00014 , H01L2224/03 , H01L2224/11
Abstract: A structure includes a metal pad, a passivation layer having a portion covering edge portions of the metal pad, and a dummy metal plate over the passivation layer. The dummy metal plate has a plurality of through-openings therein. The dummy metal plate has a zigzagged edge. A dielectric layer has a first portion overlying the dummy metal plate, second portions filling the first plurality of through-openings, and a third portion contacting the first zigzagged edge.
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67.发明授权Chip-on-wafer process control monitoring for chip-on-wafer-on-substrate packages 有权晶圆片上基板封装上的晶片过程控制监控公开(公告)号：US09581638B2
公开(公告)日：2017-02-28
申请号：US13905958
申请日：2013-05-30
Inventor： Wei-Cheng Wu , Li-Han Hsu , Sao-Ling Chiu , Shang-Yun Hou , Shin-Puu Jeng , Chen-Hua Lin
CPC classification number: H01L22/14 , G01R1/07314 , G01R31/265 , G01R31/2884 , H01L22/12 , H01L22/32 , H01L24/17 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/16055 , H01L2224/16113 , H01L2224/16145 , H01L2224/16146 , H01L2224/16227 , H01L2224/16235 , H01L2224/1713 , H01L2225/06513 , H01L2225/06541 , H01L2225/06596
Abstract: An embodiment method includes providing a standardized testing structure design for a chip-on-wafer (CoW) structure, wherein the standardized testing structure design comprises placing a testing structure in a pre-selected area a top die in the CoW structure, and electrically testing a plurality of microbumps in the CoW structure by applying a universal testing probe card to the testing structure.
Abstract translation: 一种实施方式包括提供晶片芯片（CoW）结构的标准化测试结构设计，其中标准化测试结构设计包括将测试结构放置在CoW结构中的顶部模具的预选区域内，并且电测试 通过在测试结构上应用通用测试探针卡，在CoW结构中的多个微胶片。
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公开(公告)号：US09502343B1
公开(公告)日：2016-11-22
申请号：US14858558
申请日：2015-09-18
Inventor： Cheng-Hsien Hsieh , Hsien-Wei Chen , Chi-Hsi Wu , Chen-Hua Yu , Der-Chyang Yeh , Li-Han Hsu , Wei-Cheng Wu
IPC: H01L23/52 , H01L23/498 , H01L23/31
CPC classification number: H01L23/49838 , H01L23/3171 , H01L23/3192 , H01L23/498 , H01L23/49827 , H01L23/522 , H01L23/528 , H01L23/5329 , H01L23/585 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/05572 , H01L2224/05666 , H01L2224/05681 , H01L2224/11849 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/94 , H01L2924/10252 , H01L2924/10253 , H01L2924/10271 , H01L2924/1032 , H01L2924/10336 , H01L2924/10337 , H01L2924/10338 , H01L2924/10339 , H01L2924/10342 , H01L2924/10351 , H01L2924/14 , H01L2924/3512 , H01L2924/014 , H01L2924/00014 , H01L2224/03 , H01L2224/11
Abstract: A structure includes a metal pad, a passivation layer having a portion covering edge portions of the metal pad, and a dummy metal plate over the passivation layer. The dummy metal plate has a plurality of through-openings therein. The dummy metal plate has a zigzagged edge. A dielectric layer has a first portion overlying the dummy metal plate, second portions filling the first plurality of through-openings, and a third portion contacting the first zigzagged edge.
Abstract translation: 一种结构包括金属焊盘，具有覆盖金属焊盘的边缘部分的部分的钝化层以及钝化层上的虚设金属板。 虚拟金属板在其中具有多个通孔。 虚拟金属板具有锯齿形边。 电介质层具有覆盖在虚拟金属板上的第一部分，填充第一多个通孔的第二部分和与第一锯齿状边缘接触的第三部分。
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公开(公告)号：US20160283639A1
公开(公告)日：2016-09-29
申请号：US15174795
申请日：2016-06-06
Inventor： Tzu-Yu Wang , Wei-Cheng Wu , Kuo-Ching Hsu , Shang-Yun Hou , Shin-Puu Jeng
IPC: G06F17/50
CPC classification number: G06F17/5077 , G06F17/5009 , G06F17/5081 , G06F2217/02 , G06F2217/06 , G06F2217/08 , G06F2217/38 , G06F2217/40 , H01L24/11 , H01L24/13 , H01L2224/13005 , H01L2224/16227 , H01L2924/15311
Abstract: Semiconductor device design methods and conductive bump pattern enhancement methods are disclosed. In some embodiments, a method of designing a semiconductor device includes designing a conductive bump pattern design, and implementing a conductive bump pattern enhancement algorithm on the conductive bump pattern design to create an enhanced conductive bump pattern design. A routing pattern is designed based on the enhanced conductive bump pattern design. A design rule checking (DRC) procedure is performed on the routing pattern.
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70.发明申请Semiconductor Device Packages, Packaging Methods, and Packaged Semiconductor Devices 有权半导体器件封装，封装方法和封装半导体器件公开(公告)号：US20160013138A1
公开(公告)日：2016-01-14
申请号：US14755700
申请日：2015-06-30
Inventor： Hsien-Wei Chen , Chi-Hsi Wu , Chen-Hua Yu , Der-Chyang Yeh , Wei-Cheng Wu , Chien-Fu Tseng
IPC: H01L23/00 , H01L23/31 , H01L21/768 , H01L21/56 , H01L21/78 , H01L23/12 , H01L23/522
CPC classification number: H01L21/568 , H01L21/56 , H01L21/561 , H01L21/565 , H01L21/6835 , H01L21/76838 , H01L21/78 , H01L23/12 , H01L23/3128 , H01L23/49816 , H01L23/49827 , H01L23/5389 , H01L23/544 , H01L23/562 , H01L23/585 , H01L24/06 , H01L24/19 , H01L24/20 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2221/68372 , H01L2223/5442 , H01L2223/54426 , H01L2223/54486 , H01L2224/04042 , H01L2224/04105 , H01L2224/12105 , H01L2224/2518 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/97 , H01L2225/0651 , H01L2225/06568 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/00014 , H01L2924/14 , H01L2924/1431 , H01L2924/1433 , H01L2924/1434 , H01L2924/1436 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , H01L2924/18165 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/05599 , H01L2224/85399
Abstract: Semiconductor device packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region and a molding material around the integrated circuit die mounting region. An interconnect structure is over the molding material and the integrated circuit die mounting region. A protection pattern is in a perimeter region of the package around the interconnect structure. The protection pattern includes a first conductive feature that is vertical within the package near a second conductive feature. The first conductive feature has a first width, and the second conductive feature has a second width. The second width is greater than the first width.
Abstract translation: 公开了半导体器件封装，封装方法和封装半导体器件。 在一些实施例中，用于半导体器件的封装包括集成电路管芯安装区域和围绕集成电路管芯安装区域的成型材料。 互连结构在成型材料和集成电路管芯安装区域之上。 保护图案位于互连结构周围的封装的周边区域中。 保护图案包括在第二导电特征附近的封装内的垂直的第一导电特征。 第一导电特征具有第一宽度，并且第二导电特征具有第二宽度。 第二宽度大于第一宽度。
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