公开(公告)号：US20180285268A1

公开(公告)日：2018-10-04

申请号：US15475197

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Kunal Kishore Korgaonkar ,  Ishwar S. Bhati ,  Huichu Liu ,  Jayesh Gaur ,  Sasikanth Manipatruni ,  Sreenivas Subramoney ,  Tanay Karnik ,  Hong Wang ,  Ian A. Young

IPC: G06F12/0811 ,  G06F12/0808 ,  G06F12/1045 ,  G06F13/40

Abstract: In one embodiment, a processor comprises a processing core, a last level cache (LLC), and a mid-level cache. The mid-level cache is to determine that an idle indicator has been set, wherein the idle indicator is set based on an amount of activity at the LLC, and based on the determination that the idle indicator has been set, identify a first cache line to be evicted from a first set of cache lines of the mid-level cache and send a request to write the first cache line to the LLC.

公开(公告)号：US10062731B2

公开(公告)日：2018-08-28

申请号：US15523324

申请日：2014-12-26

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Ian A. Young

IPC: H03K19/20 ,  H01L27/22 ,  H03K19/18 ,  H03K19/173

CPC classification number: H01L27/22 ,  H01L43/00 ,  H03K19/173 ,  H03K19/18

Abstract: An apparatus including a spin to charge conversion node; and a charge to spin conversion node, wherein an input to the spin to charge conversion node produces an output at the charge to spin conversion node. An apparatus including a magnet including an input node and output node, the input node including a capacitor operable to generate magnetic response in the magnet and the output node including at least one spin to charge conversion material. A method including injecting a spin current from a first magnet; converting the spin current into a charge current operable to produce a magnetoelectric interaction with a second magnet; and changing a direction of magnetization of the second magnet in response to the magnetoelectric interaction. A method including injecting a spin current from an input node of a magnet; and converting the spin current into a charge current at an output node of the magnet.

公开(公告)号：US20180240583A1

公开(公告)日：2018-08-23

申请号：US15751111

申请日：2015-09-09

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Anurag Chaudhry ,  Ian A. Young

IPC: H01F10/32 ,  H01L43/08 ,  G11C11/16 ,  H01L43/02 ,  H01L43/10 ,  H03K19/18 ,  H01L43/12 ,  H01F41/32

CPC classification number: H01F10/3254 ,  G11C11/161 ,  G11C11/1675 ,  G11C11/18 ,  H01F10/3272 ,  H01F10/3286 ,  H01F10/329 ,  H01F41/32 ,  H01L27/228 ,  H01L43/00 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H03K19/18 ,  H03K19/23

Abstract: Described is an apparatus which comprises: an input ferromagnet to receive a first charge current and to produce a first spin current; a first layer configured to convert the first spin current to a second charge current via spin orbit coupling (SOC), wherein at least a part of the first layer is coupled to the input ferromagnet; and a second layer configured to convert the second charge current to a second spin current via spin orbit coupling (SOC).

公开(公告)号：US20180232311A1

公开(公告)日：2018-08-16

申请号：US15430765

申请日：2017-02-13

Applicant: INTEL CORPORATION

Inventor： Ishwar S. Bhati ,  Huichu Liu ,  Jayesh Gaur ,  Kunal Korgaonkar ,  Sasikanth Manipatruni ,  Sreenivas Subramoney ,  Tanay Karnik ,  Hong Wang ,  Ian A. Young

IPC: G06F12/0831 ,  G06F12/0875 ,  G06F12/0811

CPC classification number: G06F13/1642 ,  G06F12/0811

Abstract: A processor includes a processing core and a cache controller including a read queue and a separate write queue. The read queue is to buffer read requests of the processing core to a non-volatile memory, last level cache (NVM-LLC), and the write queue is to buffer write requests to the NVM-LLC. The cache controller is to detect whether the write queue is full. The cache controller further prioritizes a first order of sending requests to the NVM-LLC when the write queue contains an empty slot, the first order specifying a first pattern of sending the read requests before the write requests, and prioritizes a second order of sending requests to the NVM-LLC in response to a determination that the write queue is full, the second order specifying a second pattern of alternating between sending a write request from the write queue and a read request from the read queue.

公开(公告)号：US09985611B2

公开(公告)日：2018-05-29

申请号：US14922072

申请日：2015-10-23

Applicant: Intel Corporation

Inventor： Daniel H. Morris ,  Uygar E. Avci ,  Ian A. Young

IPC: H03K3/356 ,  H01L29/66 ,  H03K3/012 ,  H03K3/3562

CPC classification number: H03K3/356113 ,  H01L29/66977 ,  H03K3/012 ,  H03K3/35625

Abstract: Described is an apparatus which comprises: a first p-type Tunneling Field-Effect Transistor (TFET); a first n-type TFET coupled in series with the first p-type TFET; a first node coupled to gate terminals of the first p-type and n-type TFETs; a first clock node coupled to a source terminal of the first TFET, the first clock node is to provide a first clock; and a second clock node coupled to a source terminal of the second TFET, the second clock node is to provide a second clock.

公开(公告)号：US09911835B2

公开(公告)日：2018-03-06

申请号：US15410548

申请日：2017-01-19

Applicant: Intel Corporation

Inventor： Roza Kotlyar ,  Stephen M. Cea ,  Gilbert Dewey ,  Benjamin Chu-Kung ,  Uygar E. Avci ,  Rafael Rios ,  Anurag Chaudhry ,  Thomas D. Linton, Jr. ,  Ian A. Young ,  Kelin J. Kuhn

IPC: H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L29/739 ,  H01L29/161 ,  H01L29/06 ,  H01L29/24 ,  H01L29/267 ,  H01L27/092 ,  H01L29/04 ,  H01L29/10 ,  H01L29/165 ,  H01L29/20 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/66977 ,  H01L27/092 ,  H01L29/045 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/20 ,  H01L29/24 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/7391 ,  H01L29/7842 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78642 ,  H01L29/78684 ,  H01L29/78696

Abstract: Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region disposed above a substrate. The homojunction active region includes a relaxed Ge or GeSn body having an undoped channel region therein. The homojunction active region also includes doped source and drain regions disposed in the relaxed Ge or GeSn body, on either side of the channel region. The TFET also includes a gate stack disposed on the channel region, between the source and drain regions. The gate stack includes a gate dielectric portion and gate electrode portion.

公开(公告)号：US09847475B2

公开(公告)日：2017-12-19

申请号：US15119380

申请日：2014-03-25

Applicant: Intel Corporation

Inventor： Dmitri E. Nikonov ,  Sasikanth Manipatruni, II ,  Ian A. Young

IPC: H01L43/08 ,  H01L43/10

CPC classification number: H01L43/08 ,  H01L43/10 ,  H03K19/18 ,  H03K19/23

Abstract: Described is an apparatus which comprises: first, second, and third free magnetic layers; a first metal layer of first material coupled to the first and third free magnetic layers; and a second metal layer of second material different from the first material, the second metal layer coupled to the second and third free magnetic layers. Described is an STT majority gate device which comprises: a free magnetic layer in a ring; and first, second, third, and fourth free magnetic layers coupled to the free magnetic layer.

公开(公告)号：US09842643B2

公开(公告)日：2017-12-12

申请号：US15282484

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Daniel H. Morris ,  Uygar E. Avci ,  Rafael Rios ,  Ian A. Young

IPC: G11C11/40 ,  G11C11/419 ,  H03K3/356 ,  G11C11/412 ,  G11C5/14

CPC classification number: G11C11/419 ,  G11C5/145 ,  G11C11/412 ,  H01L27/1104 ,  H03K3/356104

Abstract: Embodiments include apparatuses, methods, and systems for a circuit to shift a voltage level. The circuit may include a first inverter that includes a first transistor coupled to pass a low voltage signal and a second inverter coupled to receive the low voltage signal. The circuit may further include a second transistor coupled to receive the low voltage signal from the second inverter to serve as a feedback device and produce a high voltage signal. In embodiments, the first transistor conducts asymmetrically to prevent crossover of the high voltage signal into the low voltage domain. A low voltage memory array is also described. In embodiments, the circuit to shift a voltage level may assist communication between a logic component including the low voltage memory array of a low voltage domain and a logic component of a high voltage domain. Additional embodiments may also be described.

公开(公告)号：US20170163275A1

公开(公告)日：2017-06-08

申请号：US15300266

申请日：2014-06-18

Applicant: Intel Corporation

Inventor： Sasikanth Sasi Manipatruni ,  George I. Bourianoff ,  Dmitri E. Nikonov ,  Ian A. Young

IPC: H03L7/26 ,  G11C11/16 ,  H01L43/08

CPC classification number: H03L7/26 ,  G11C11/161 ,  G11C11/1675 ,  G11C11/18 ,  H01L43/08 ,  H03B15/006

Abstract: Described is an oscillating apparatus which comprises: an interconnect with spin-coupling material (e.g., Spin Hall Effect (SHE) material); and a magnetic stack having two magnetic layers such that one of the magnetic layers is coupled to the interconnect, wherein each of the two magnetic layers have respective magnetization directions to cause the magnetic stack to oscillate.

公开(公告)号：US09559698B2

公开(公告)日：2017-01-31

申请号：US14906025

申请日：2013-09-30

Applicant: Intel Corporation

Inventor： Dmitri E. Nikonov ,  Sasikanth Manipatruni ,  Michael Kishinevsky ,  Ian A. Young

IPC: H03K19/16 ,  H01L29/66 ,  G11C11/16 ,  H03K19/18 ,  H01L43/08 ,  H01L27/22 ,  H01L43/02

CPC classification number: H03K19/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  H01L27/222 ,  H01L29/66984 ,  H01L43/02 ,  H01L43/08 ,  H03K19/18

Abstract: An embodiment includes a C-element logic gate implemented as a spin logic device that provides a compact and low-power implementation of asynchronous logic by implementing a C-element with spintronic technology. An embodiment includes a first nanopillar including a first contact and a first fixed magnetic layer; a second nanopillar including a second contact and a second fixed magnetic layer; and a third nanopillar including a third contact, a tunnel barrier, and a third fixed magnetic layer; wherein (a) the first, second, and third nanopillars are all formed over a free magnetic layer, and (b) the third fixed magnetic layer, the tunnel barrier, and the free magnetic layer form a magnetic tunnel junction (MTJ). Other embodiments are described herein.

Abstract translation: 实施例包括被实现为自旋逻辑器件的C元件逻辑门，其通过使用自旋电子技术实现C元件来提供异步逻辑的紧凑和低功率实施。 一个实施例包括第一纳米柱，其包括第一接触和第一固定磁性层; 包括第二接触和第二固定磁性层的第二纳米柱; 以及包括第三接触件，隧道势垒和第三固定磁性层的第三纳米柱; 其中（a）第一，第二和第三纳米锥都形成在自由磁性层上，并且（b）第三固定磁性层，隧道势垒和自由磁性层形成磁性隧道结（MTJ）。 本文描述了其它实施例。