公开(公告)号：US20180181329A1

公开(公告)日：2018-06-28

申请号：US15392638

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Ishwar S. Bhati ,  Udit Dhawan ,  Jayesh Gaur ,  Sreenivas Subramoney

IPC: G06F3/06 ,  G06F12/0897

CPC classification number: G06F12/0897 ,  G06F9/3824 ,  G06F12/0811 ,  G06F2212/1041 ,  G06F2212/1056 ,  G06F2212/302

Abstract: Processor, apparatus, and method for reordering a stream of memory access requests to establish locality are described herein. One embodiment of a method includes: storing in a request queue memory access requests generated by a plurality of execution units, the memory access requests comprising a first request to access a first memory page in a memory and a second request to access a second memory page in the memory; maintaining a list of unique memory pages, each unique memory page associated with one or more memory access requests stored the request queue and is to be accessed by the one or more memory access requests; selecting a current memory page from the list of unique memory pages; and dispatching from the request queue to the memory, all memory access requests associated with the current memory page before any other memory access request in the request queue is dispatched.

公开(公告)号：US10331582B2

公开(公告)日：2019-06-25

申请号：US15430765

申请日：2017-02-13

Applicant: INTEL CORPORATION

Inventor： Ishwar S. Bhati ,  Huichu Liu ,  Jayesh Gaur ,  Kunal Korgaonkar ,  Sasikanth Manipatruni ,  Sreenivas Subramoney ,  Tanay Karnik ,  Hong Wang ,  Ian A. Young

IPC: G06F13/16 ,  G06F12/0811

Abstract: A processor includes a processing core and a cache controller including a read queue and a separate write queue. The read queue is to buffer read requests of the processing core to a non-volatile memory, last level cache (NVM-LLC), and the write queue is to buffer write requests to the NVM-LLC. The cache controller is to detect whether the write queue is full. The cache controller further prioritizes a first order of sending requests to the NVM-LLC when the write queue contains an empty slot, the first order specifying a first pattern of sending the read requests before the write requests, and prioritizes a second order of sending requests to the NVM-LLC in response to a determination that the write queue is full, the second order specifying a second pattern of alternating between sending a write request from the write queue and a read request from the read queue.

公开(公告)号：US20180285268A1

公开(公告)日：2018-10-04

申请号：US15475197

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Kunal Kishore Korgaonkar ,  Ishwar S. Bhati ,  Huichu Liu ,  Jayesh Gaur ,  Sasikanth Manipatruni ,  Sreenivas Subramoney ,  Tanay Karnik ,  Hong Wang ,  Ian A. Young

IPC: G06F12/0811 ,  G06F12/0808 ,  G06F12/1045 ,  G06F13/40

Abstract: In one embodiment, a processor comprises a processing core, a last level cache (LLC), and a mid-level cache. The mid-level cache is to determine that an idle indicator has been set, wherein the idle indicator is set based on an amount of activity at the LLC, and based on the determination that the idle indicator has been set, identify a first cache line to be evicted from a first set of cache lines of the mid-level cache and send a request to write the first cache line to the LLC.

公开(公告)号：US20180232311A1

公开(公告)日：2018-08-16

申请号：US15430765

申请日：2017-02-13

Applicant: INTEL CORPORATION

Inventor： Ishwar S. Bhati ,  Huichu Liu ,  Jayesh Gaur ,  Kunal Korgaonkar ,  Sasikanth Manipatruni ,  Sreenivas Subramoney ,  Tanay Karnik ,  Hong Wang ,  Ian A. Young

IPC: G06F12/0831 ,  G06F12/0875 ,  G06F12/0811

CPC classification number: G06F13/1642 ,  G06F12/0811

Abstract: A processor includes a processing core and a cache controller including a read queue and a separate write queue. The read queue is to buffer read requests of the processing core to a non-volatile memory, last level cache (NVM-LLC), and the write queue is to buffer write requests to the NVM-LLC. The cache controller is to detect whether the write queue is full. The cache controller further prioritizes a first order of sending requests to the NVM-LLC when the write queue contains an empty slot, the first order specifying a first pattern of sending the read requests before the write requests, and prioritizes a second order of sending requests to the NVM-LLC in response to a determination that the write queue is full, the second order specifying a second pattern of alternating between sending a write request from the write queue and a read request from the read queue.