公开(公告)号：US11782755B2

公开(公告)日：2023-10-10

申请号：US16729026

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Renji Thomas ,  Chris Binns ,  Pietro Mercati ,  Jianfang Zhu ,  Ashraf H. Wadaa ,  Michael Kishinevsky ,  Ahmed Shams

IPC: G06F9/46 ,  G06F9/48 ,  G06F11/34 ,  G06F30/20 ,  G06F9/38

CPC classification number: G06F9/4881 ,  G06F9/3836 ,  G06F11/3433 ,  G06F30/20

Abstract: An apparatus comprising: a model to generate adjusted tuning parameters of a thread scheduling policy based on a tradeoff indication value of a target system; and a workload monitor to: execute a workload based on the thread scheduling policy; obtain a performance score and a power score from the target system based on execution of the workload, the performance score and the power score corresponding to a tradeoff indication value; compare the tradeoff indication value to a criterion; and based on the comparison, initiate the model to re-adjust the adjusted tuning parameters.

公开(公告)号：US09559698B2

公开(公告)日：2017-01-31

申请号：US14906025

申请日：2013-09-30

Applicant: Intel Corporation

Inventor： Dmitri E. Nikonov ,  Sasikanth Manipatruni ,  Michael Kishinevsky ,  Ian A. Young

IPC: H03K19/16 ,  H01L29/66 ,  G11C11/16 ,  H03K19/18 ,  H01L43/08 ,  H01L27/22 ,  H01L43/02

CPC classification number: H03K19/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  H01L27/222 ,  H01L29/66984 ,  H01L43/02 ,  H01L43/08 ,  H03K19/18

Abstract: An embodiment includes a C-element logic gate implemented as a spin logic device that provides a compact and low-power implementation of asynchronous logic by implementing a C-element with spintronic technology. An embodiment includes a first nanopillar including a first contact and a first fixed magnetic layer; a second nanopillar including a second contact and a second fixed magnetic layer; and a third nanopillar including a third contact, a tunnel barrier, and a third fixed magnetic layer; wherein (a) the first, second, and third nanopillars are all formed over a free magnetic layer, and (b) the third fixed magnetic layer, the tunnel barrier, and the free magnetic layer form a magnetic tunnel junction (MTJ). Other embodiments are described herein.

Abstract translation: 实施例包括被实现为自旋逻辑器件的C元件逻辑门，其通过使用自旋电子技术实现C元件来提供异步逻辑的紧凑和低功率实施。 一个实施例包括第一纳米柱，其包括第一接触和第一固定磁性层; 包括第二接触和第二固定磁性层的第二纳米柱; 以及包括第三接触件，隧道势垒和第三固定磁性层的第三纳米柱; 其中（a）第一，第二和第三纳米锥都形成在自由磁性层上，并且（b）第三固定磁性层，隧道势垒和自由磁性层形成磁性隧道结（MTJ）。 本文描述了其它实施例。

公开(公告)号：US20180137668A1

公开(公告)日：2018-05-17

申请号：US15811459

申请日：2017-11-13

Applicant: Intel Corporation

Inventor： Pietro Mercati ,  Raid Ayoub ,  Michael Kishinevsky ,  Eric C. Samson ,  Marc Beuchat ,  Francesco Paterna

IPC: G06T15/00 ,  G06T15/80

CPC classification number: G06T15/005 ,  G06F1/206 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F8/41 ,  G06F8/65 ,  G06T15/80 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/42

Abstract: Methods and apparatus relating to techniques for dynamically selecting optimum graphics logic frequency and/or graphics logic power gating configuration are described. In an embodiment, multi-rate control logic determines processor active slice count and processor frequency based at least in part on a target Frames Per Second (FPS) value and a current FPS value. The multi-rate control logic includes slow rate control logic to determine slice gating and operating frequency and a fast rate control logic to determine operating frequency of the processor. Other embodiments are also disclosed and claimed.