-
公开(公告)号：US20150357301A1
公开(公告)日：2015-12-10
申请号：US14828147
申请日：2015-08-17
Inventor： Guan-Yu Chen , Yu-Wei Lin , Yu-Jen Tseng , Tin-Hao Kuo , Chen-Shien Chen
IPC: H01L23/00
CPC classification number: H01L24/02 , H01L21/4853 , H01L21/76885 , H01L23/49811 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/02125 , H01L2224/02141 , H01L2224/02145 , H01L2224/0215 , H01L2224/0401 , H01L2224/05114 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05647 , H01L2224/10125 , H01L2224/11013 , H01L2224/11019 , H01L2224/1112 , H01L2224/11462 , H01L2224/11472 , H01L2224/13012 , H01L2224/13015 , H01L2224/13017 , H01L2224/13023 , H01L2224/13026 , H01L2224/1308 , H01L2224/13082 , H01L2224/13083 , H01L2224/13111 , H01L2224/13116 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13166 , H01L2224/13551 , H01L2224/13564 , H01L2224/13565 , H01L2224/1357 , H01L2224/13582 , H01L2224/136 , H01L2224/13686 , H01L2224/1369 , H01L2224/14051 , H01L2224/16148 , H01L2224/16227 , H01L2224/16238 , H01L2224/16503 , H01L2224/81007 , H01L2224/81143 , H01L2224/81191 , H01L2224/81203 , H01L2224/81424 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/8181 , H01L2224/81895 , H01L2224/8192 , H01L2224/81948 , H01L2225/06513 , H01L2924/04941 , H01L2924/07025 , H01L2924/181 , H01L2924/301 , H01L2924/35 , Y10T29/49144 , H01L2924/00014 , H01L2924/014 , H01L2924/05432 , H01L2924/053 , H01L2924/00 , H01L2924/00012
Abstract: An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal bump on the under bump metallurgy feature, and a substrate trace on a substrate, the substrate trace coupled to the metal bump through a solder joint and intermetallic compounds, a ratio of a first cross sectional area of the intermetallic compounds to a second cross sectional area of the solder joint greater than forty percent.
Abstract translation: 轨迹（BOT）结构上的实施例凸块包括由集成电路支撑的接触元件，电耦合到接触元件的凸块下金属（UBM）特征，凸起下金属冶金特征上的金属凸块，以及衬底迹线 衬底，通过焊接接头和金属间化合物耦合到金属凸块的衬底迹线，金属间化合物的第一横截面积与焊料接头的第二横截面积的比率大于百分之四十。
-
公开(公告)号：US09165796B2
公开(公告)日：2015-10-20
申请号：US14459047
申请日：2014-08-13
Inventor： Yen-Liang Lin , Chang-Chia Huang , Tin-Hao Kuo , Sheng-Yu Wu , Chen-Shien Chen
CPC classification number: H01L21/563 , H01L23/3157 , H01L23/49816 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/81 , H01L2224/13023 , H01L2224/13082 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/16237 , H01L2224/16238 , H01L2224/26175 , H01L2224/2929 , H01L2224/29386 , H01L2224/321 , H01L2224/32225 , H01L2224/73204 , H01L2224/81024 , H01L2224/81191 , H01L2224/81815 , H01L2224/83102 , H01L2924/15311 , H01L2924/35121 , H01L2924/37001 , H01L2224/16225 , H01L2924/00 , H01L2924/00014 , H01L2224/2919 , H01L2924/0665 , H01L2924/05442 , H01L2924/00012
Abstract: Methods and apparatuses for a attaching a first substrate to a second substrate are provided. In some embodiments, a first substrate has a protective layer, such as a solder mask, around a die attach area, at which a second substrate is attached. A keep-out region (e.g., an area between the second substrate and the protective layer) is a region around the second substrate in which the protective layer is not formed or removed. The keep-out region is sized such that a sufficient gap exists between the second substrate and the protective layer to place an underfill between the first substrate and the second substrate while reducing or preventing voids and while allowing traces in the keep-out region to be covered by the underfill.
Abstract translation: 提供了将第一基板附接到第二基板的方法和装置。 在一些实施例中，第一基板在芯片附着区域周围具有保护层，例如焊接掩模，第二基板在该附着区域附接。 保留区域（例如，第二基板和保护层之间的区域）是不形成或去除保护层的第二基板周围的区域。 保持区域的尺寸使得在第二基板和保护层之间存在足够的间隙，以在第一基板和第二基板之间放置底部填充物，同时减少或防止空隙，并且同时允许在外部区域中的迹线为 由底部填充物覆盖。
-
53.发明授权Packaging and function tests for package-on-package and system-in-package structures 有权包装封装和系统级封装结构的封装和功能测试公开(公告)号：US09040350B2
公开(公告)日：2015-05-26
申请号：US14277197
申请日：2014-05-14
Inventor： Hao-Juin Liu , Chita Chuang , Ching-Wen Hsiao , Chen-Shien Chen , Chen-Cheng Kuo , Chih-Hua Chen
CPC classification number: H01L22/20 , H01L22/14 , H01L23/3128 , H01L23/48 , H01L24/97 , H01L25/105 , H01L25/50 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2224/97 , H01L2225/1023 , H01L2225/1058 , H01L2924/15311 , H01L2924/15331 , H01L2224/81 , H01L2924/00012 , H01L2924/00
Abstract: A method includes placing a plurality of bottom units onto a jig, wherein the plurality of bottom units is not sawed apart and forms an integrated component. Each of the plurality of bottom units includes a package substrate and a die bonded to the package substrate. A plurality of upper component stacks is placed onto the plurality of bottom units, wherein solder balls are located between the plurality of upper component and the plurality of bottom units. A reflow is performed to join the plurality of upper component stacks with respective ones of the plurality of bottom units through the solder balls.
Abstract translation: 一种方法包括将多个底部单元放置在夹具上，其中多个底部单元没有锯切并形成一个集成部件。 多个底部单元中的每一个包括封装基板和结合到封装基板的管芯。 多个上部组件堆放在多个底部单元上，其中焊球位于多个上部组件和多个底部单元之间。 执行回流以通过焊球将多个上部部件堆叠与多个底部单元中的相应的底部单元接合。
-
54.发明申请Methods and Apparatus for Package on Package Devices with Reversed Stud Bump Through Via Interconnections 审中-公开封装器件封装器件的方法和装置，具有反相螺柱通过互连件突出公开(公告)号：US20150072476A1
公开(公告)日：2015-03-12
申请号：US14546777
申请日：2014-11-18
Inventor： Yen-Chang Hu , Chen-Shien Chen , Tin-Hao Kuo , Chih-Hua Chen , Ching-Wen Hsiao
CPC classification number: H01L25/50 , H01L23/49816 , H01L23/5389 , H01L24/11 , H01L24/19 , H01L24/20 , H01L24/81 , H01L25/0657 , H01L25/105 , H01L2224/0231 , H01L2224/0401 , H01L2224/04105 , H01L2224/11002 , H01L2224/11003 , H01L2224/1134 , H01L2224/12105 , H01L2224/45144 , H01L2224/45147 , H01L2224/73267 , H01L2225/06541 , H01L2225/06565 , H01L2225/1035 , H01L2225/1058 , H01L2924/00011 , H01L2924/00014 , H01L2924/01047 , H01L2924/01322 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , Y02P80/30 , H01L2924/00 , H01L2224/48 , H01L2224/81805
Abstract: Methods and apparatus for package on package structures having stud bump through via interconnections. A structure includes an interconnect layer having a plurality of through via assemblies each including at least one stud bump are formed on conductive pads; and encapsulant surrounding the through via assembly, a first redistribution layer formed over a surface of the encapsulant and coupled to the through via assemblies and carrying connectors, and a second redistribution layer over interconnect layer at the other end of the through via assemblies, the through via assemblies extending vertically through the interconnect layer. In an embodiment the interconnect layer is mounted using the connectors to a lower package substrate to form a package on package structure. A first integrated circuit device may be mounted on the second redistribution layer of the interconnect layer. Methods for forming the interconnect layer and the package on package structures are disclosed.
Abstract translation: 封装结构上的封装结构的方法和装置，其具有穿过通孔互连的凸块凸块。 一种结构包括具有多个通孔组件的互连层，每个穿孔组件包括至少一个柱形突起，其在导电垫上形成; 以及围绕所述通孔组件的密封剂，形成在所述密封剂的表面上并且连接到所述通孔组件和承载连接器的第一再分布层，以及在所述通孔组件的另一端处的互连层上的第二再分布层， 通过组件垂直延伸穿过互连层。 在一个实施例中，使用连接器将互连层安装到下封装衬底以形成封装结构上的封装。 第一集成电路器件可以安装在互连层的第二再分配层上。 公开了在封装结构上形成互连层和封装的方法。
-
公开(公告)号：US20150069595A1
公开(公告)日：2015-03-12
申请号：US14547019
申请日：2014-11-18
Inventor： Chih-Hua Chen , Chen-Shien Chen , Ching-Wen Hsiao , Ming Hung Tseng
IPC: H01L25/18 , H01L23/498 , H01L23/48
CPC classification number: H01L25/18 , H01L21/561 , H01L21/568 , H01L21/6836 , H01L23/481 , H01L23/49838 , H01L23/5389 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/19 , H01L24/20 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/85 , H01L24/92 , H01L24/96 , H01L25/0657 , H01L25/105 , H01L2221/68327 , H01L2221/68331 , H01L2221/68368 , H01L2221/68381 , H01L2224/0401 , H01L2224/04105 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/12105 , H01L2224/13116 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2224/211 , H01L2224/215 , H01L2224/221 , H01L2224/2518 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48228 , H01L2224/48235 , H01L2224/48624 , H01L2224/48644 , H01L2224/48647 , H01L2224/48724 , H01L2224/48744 , H01L2224/48747 , H01L2224/48824 , H01L2224/48844 , H01L2224/48847 , H01L2224/73265 , H01L2224/81011 , H01L2224/81024 , H01L2224/81203 , H01L2224/81815 , H01L2224/82101 , H01L2224/82106 , H01L2224/85205 , H01L2224/92 , H01L2224/96 , H01L2225/0651 , H01L2225/06568 , H01L2225/1023 , H01L2225/1035 , H01L2225/1058 , H01L2924/01322 , H01L2924/12042 , H01L2924/1434 , H01L2924/15311 , H01L2924/15787 , H01L2924/181 , H01L2924/351 , H01L2224/48227 , H01L2924/00012 , H01L2924/0105 , H01L2924/00014 , H01L2924/01029 , H01L2924/01013 , H01L2924/01079 , H01L2924/01074 , H01L2224/19 , H01L2224/11 , H01L2224/81 , H01L22/14 , H01L21/78 , H01L25/50 , H01L2924/00
Abstract: A component package and a method of forming are provided. A first component package may include a first semiconductor device having a pair of interposers attached thereto on opposing sides of the first semiconductor device. Each interposer may include conductive traces formed therein to provide electrical coupling to conductive features formed on the surfaces of the respective interposers. A plurality of through vias may provide for electrically connecting the interposers to one another. A first interposer may provide for electrical connections to a printed circuit board or subsequent semiconductor device. A second interposer may provide for electrical connections to a second semiconductor device and a second component package. The first and second component packages may be combined to form a Package-on-Package (“PoP”) structure.
Abstract translation: 提供了组件封装和成形方法。 第一部件封装可以包括在第一半导体器件的相对侧上附接有一对插入件的第一半导体器件。 每个插入器可以包括形成在其中的导电迹线以提供与形成在各个插入件的表面上的导电特征的电耦合。 多个通孔可以提供将插入件彼此电连接。 第一插入器可以提供到印刷电路板或随后的半导体器件的电连接。 第二插入器可以提供到第二半导体器件和第二部件封装的电连接。 可以组合第一和第二组件封装以形成封装封装（“PoP”）结构。
-
Patent Agency Ranking
公开(公告)号：US20150037936A1
公开(公告)日：2015-02-05
申请号：US14521233
申请日：2014-10-22
Inventor： Wen-Wei Shen , Chen-Shien Chen , Chen-Cheng Kuo , Ming-Fa Chen , Rung-De Wang
IPC: H01L23/00
CPC classification number: H01L24/16 , H01L23/3157 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/03614 , H01L2224/0401 , H01L2224/05017 , H01L2224/05023 , H01L2224/05124 , H01L2224/05139 , H01L2224/05147 , H01L2224/05155 , H01L2224/05568 , H01L2224/05572 , H01L2224/05647 , H01L2224/05666 , H01L2224/1146 , H01L2224/11823 , H01L2224/11831 , H01L2224/1191 , H01L2224/13005 , H01L2224/13018 , H01L2224/13019 , H01L2224/13076 , H01L2224/1308 , H01L2224/13083 , H01L2224/13111 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13565 , H01L2224/1357 , H01L2224/1369 , H01L2224/16145 , H01L2224/16148 , H01L2224/16238 , H01L2224/81193 , H01L2224/81345 , H01L2224/81801 , H01L2224/81815 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01028 , H01L2924/01029 , H01L2924/01046 , H01L2924/01079 , H01L2924/01322 , H01L2924/05042 , H01L2924/10253 , H01L2924/14 , H01L2924/35 , Y10T428/12361 , Y10T428/12396 , H01L2924/00 , H01L2924/00012 , H01L2924/01047 , H01L2924/206 , H01L2224/05552
Abstract: A device includes a work piece including a metal bump; and a dielectric layer having a portion directly over the metal bump. The metal bump and a surface of the portion of the dielectric layer form an interface. A metal finish is formed over and contacting the metal bump. The metal finish extends from over the dielectric layer to below the interface.
Abstract translation: 一种装置包括：包括金属凸块的工件; 以及具有直接在金属凸块上的部分的介电层。 金属凸块和电介质层部分的表面形成界面。 在金属凸块上方形成金属涂层并与金属凸块接触。 金属表面从介电层上延伸到界面的下方。
-
公开(公告)号：US20140346673A1
公开(公告)日：2014-11-27
申请号：US14459047
申请日：2014-08-13
Inventor： Yen-Liang Lin , Chang-Chia Huang , Tin-Hao Kuo , Sheng-Yu Wu , Chen-Shien Chen
CPC classification number: H01L21/563 , H01L23/3157 , H01L23/49816 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/81 , H01L2224/13023 , H01L2224/13082 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/16237 , H01L2224/16238 , H01L2224/26175 , H01L2224/2929 , H01L2224/29386 , H01L2224/321 , H01L2224/32225 , H01L2224/73204 , H01L2224/81024 , H01L2224/81191 , H01L2224/81815 , H01L2224/83102 , H01L2924/15311 , H01L2924/35121 , H01L2924/37001 , H01L2224/16225 , H01L2924/00 , H01L2924/00014 , H01L2224/2919 , H01L2924/0665 , H01L2924/05442 , H01L2924/00012
Abstract: Methods and apparatuses for a attaching a first substrate to a second substrate are provided. In some embodiments, a first substrate has a protective layer, such as a solder mask, around a die attach area, at which a second substrate is attached. A keep-out region (e.g., an area between the second substrate and the protective layer) is a region around the second substrate in which the protective layer is not formed or removed. The keep-out region is sized such that a sufficient gap exists between the second substrate and the protective layer to place an underfill between the first substrate and the second substrate while reducing or preventing voids and while allowing traces in the keep-out region to be covered by the underfill.
Abstract translation: 提供了将第一基板附接到第二基板的方法和装置。 在一些实施例中，第一基板在芯片附着区域周围具有保护层，例如焊接掩模，第二基板在该附着区域附接。 保留区域（例如，第二基板和保护层之间的区域）是第二基板周围的区域，其中未形成或去除保护层。 保持区域的尺寸使得在第二基板和保护层之间存在足够的间隙，以在第一基板和第二基板之间放置底部填充物，同时减少或防止空隙，并且同时允许在外部区域中的迹线为 由底部填充物覆盖。
-
公开(公告)号：US20140191390A1
公开(公告)日：2014-07-10
申请号：US13734573
申请日：2013-01-04
Inventor： Chita Chuang , Yao-Chun Chuang , Chih-Hua Chen , Chen-Cheng Kuo , Chen-Shien Chen
IPC: H01L23/498
CPC classification number: H01L24/05 , H01L23/3192 , H01L23/528 , H01L24/13 , H01L24/16 , H01L2224/02375 , H01L2224/03826 , H01L2224/03912 , H01L2224/0401 , H01L2224/05005 , H01L2224/05008 , H01L2224/05009 , H01L2224/05022 , H01L2224/05078 , H01L2224/05124 , H01L2224/05166 , H01L2224/05541 , H01L2224/05552 , H01L2224/05572 , H01L2224/05582 , H01L2224/05647 , H01L2224/1146 , H01L2224/1147 , H01L2224/13012 , H01L2224/1308 , H01L2224/13083 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/16 , H01L2224/16145 , H01L2224/16238 , H01L2224/81815 , H01L2924/00014 , H01L2924/206 , H01L2924/00012 , H01L2924/01047 , H01L2924/01029
Abstract: A device includes a substrate, a metal pad over the substrate, and a metal trace electrically disconnected from the metal pad. The metal pad and the metal trace are level with each other. A passivation layer includes a portion overlapping an edge portion of the metal pad. A metal pillar is overlying the metal pad, and is electrically connected to the metal pad. The metal trace has a portion overlapped by the metal pillar.
Abstract translation: 一种器件包括衬底，衬底上的金属焊盘以及与金属焊盘电连接的金属迹线。 金属焊盘和金属迹线相互平齐。 钝化层包括与金属焊盘的边缘部分重叠的部分。 金属支柱覆盖在金属垫上，并与金属垫电连接。 金属轨迹具有与金属柱重叠的部分。
-
公开(公告)号：US20140185264A1
公开(公告)日：2014-07-03
申请号：US13729902
申请日：2012-12-28
Inventor： Hsu-Hsien Chen , Chih-Hua Chen , En-Hsiang Yeh , Monsen Liu , Chen-Shien Chen
IPC: H05K7/06
CPC classification number: H01L23/3128 , H01L21/563 , H01L23/3185 , H01L25/0652 , H01L2224/16225 , H01L2224/16227 , H01L2224/32145 , H01L2224/48227 , H01L2924/15192 , H01L2924/15311 , H01L2924/15313 , H01L2924/18161 , H01L2924/19041 , H01L2924/19105
Abstract: Methods and apparatus are disclosed for a package or a package-on-package (PoP) device. An IC package or a PoP device may comprise an electrical path connecting a die and a decoupling capacitor, wherein the electrical path may have a width in a range from about 8 um to about 44 um and a length in a range from about 10 um to about 650 um. The decoupling capacitor and the die may be contained in a same package, or at different packages within a PoP device, connected by contact pads, redistribution layers (RDLs), and connectors.
Abstract translation: 公开了用于封装或封装封装（PoP）器件的方法和装置。 IC封装或PoP器件可以包括连接管芯和去耦电容器的电路径，其中电路径可以具有在约8μm至约44μm的范围内的长度，并且在约10μm至约 约650 um。 去耦电容器和管芯可以包含在相同的封装中，或者在PoP器件内的不同封装中，由接触焊盘，再分布层（RDL）和连接器连接。
-
60.发明申请Semiconductor Devices, Methods of Manufacture Thereof, and Packaged Semiconductor Devices 有权半导体器件，其制造方法和封装半导体器件公开(公告)号：US20140167253A1
公开(公告)日：2014-06-19
申请号：US13719019
申请日：2012-12-18
Inventor： Yu-Jen Tseng , Yen-Liang Lin , Tin-Hao Kuo , Chen-Shien Chen , Mirng-Ji Lii
IPC: H01L23/528 , H01L21/768 , H01L23/00 , H01L23/532
CPC classification number: H01L24/15 , H01L21/02118 , H01L21/0273 , H01L21/283 , H01L21/44 , H01L21/47 , H01L21/563 , H01L23/3142 , H01L23/3192 , H01L23/488 , H01L23/49816 , H01L23/5283 , H01L24/03 , H01L24/10 , H01L24/11 , H01L24/12 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L2224/02333 , H01L2224/0347 , H01L2224/0401 , H01L2224/05567 , H01L2224/05624 , H01L2224/1146 , H01L2224/11472 , H01L2224/13005 , H01L2224/13012 , H01L2224/13013 , H01L2224/13014 , H01L2224/13015 , H01L2224/13017 , H01L2224/13022 , H01L2224/1308 , H01L2224/13083 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13166 , H01L2224/13565 , H01L2224/1357 , H01L2224/13686 , H01L2224/16058 , H01L2224/16238 , H01L2224/73104 , H01L2224/81191 , H01L2224/81192 , H01L2224/81345 , H01L2224/81815 , H01L2224/8182 , H01L2224/83104 , H01L2224/94 , H01L2225/06513 , H01L2924/00014 , H01L2924/15787 , H01L2924/181 , H01L2924/3841 , H01L2224/11 , H01L2924/00012 , H01L2924/207 , H01L2924/01047 , H01L2924/01029 , H01L2224/05552 , H01L2924/00
Abstract: Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices are disclosed. In one embodiment, a semiconductor device includes a substrate and conductive traces disposed over the substrate. Each of the conductive traces has a bottom region proximate the substrate and a top region opposite the bottom region. The top region has a first width and the bottom region has a second width. The second width is greater than the first width.
Abstract translation: 公开了半导体器件，其制造方法和封装的半导体器件。 在一个实施例中，半导体器件包括衬底和设置在衬底上的导电迹线。 每个导电迹线具有靠近衬底的底部区域和与底部区域相对的顶部区域。 顶部区域具有第一宽度，底部区域具有第二宽度。 第二宽度大于第一宽度。
-
-
-
-
-
-
-
-
-
Search Results
357
records
(took 0.029 seconds)
