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公开(公告)号：US11723292B2
公开(公告)日：2023-08-08
申请号：US16910609
申请日：2020-06-24
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chih-Yang Chang , Wen-Ting Chu , Kuo-Chi Tu , Yu-Wen Liao , Hsia-Wei Chen , Chin-Chieh Yang , Sheng-Hung Shih , Wen-Chun You
CPC classification number: H10N70/8265 , H10B63/30 , H10N70/011 , H10N70/063 , H10N70/066 , H10N70/20 , H10N70/24 , H10N70/826 , H10N70/841 , H10N70/8833 , H10N70/021 , H10N70/023 , H10N70/026 , H10N70/028 , H10N70/041 , H10N70/043 , H10N70/046 , H10N70/061 , H10N70/068 , H10N70/231 , H10N70/235 , H10N70/245 , H10N70/25 , H10N70/253 , H10N70/257 , H10N70/801 , H10N70/821 , H10N70/823 , H10N70/828 , H10N70/8413 , H10N70/8416 , H10N70/8418 , H10N70/8613 , H10N70/8616 , H10N70/881 , H10N70/882 , H10N70/883 , H10N70/884 , H10N70/8822 , H10N70/8825 , H10N70/8828 , H10N70/8836 , H10N70/8845
Abstract: The present disclosure, in some embodiments, relates to a memory device. The memory device includes a dielectric protection layer having sidewalls defining an opening over a conductive interconnect within an inter-level dielectric (ILD) layer. A bottom electrode structure extends from within the opening to directly over the dielectric protection layer. A variable resistance layer is over the bottom electrode structure and a top electrode is over the variable resistance layer. A top electrode via is disposed on the top electrode and directly over the dielectric protection layer.
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公开(公告)号：US11201281B2
公开(公告)日：2021-12-14
申请号：US16939583
申请日：2020-07-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hsia-Wei Chen , Chih-Yang Chang , Chin-Chieh Yang , Jen-Sheng Yang , Sheng-Hung Shih , Tung-Sheng Hsiao , Wen-Ting Chu , Yu-Wen Liao , I-Ching Chen
IPC: H01L43/02 , H01L23/538 , H01L43/12 , H01L27/22 , H01L45/00 , H01L21/768 , H01L27/24 , H01L43/08
Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.
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公开(公告)号：US20200343265A1
公开(公告)日：2020-10-29
申请号：US16394207
申请日：2019-04-25
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chih-Hsiang Chang , Kuo-Chi Tu , Sheng-Hung Shih , Wen-Ting Chu , Tzu-Yu Chen , Fu-Chen Chang
Abstract: In some embodiments, the present disclosure relates to an integrated chip including one or more lower interconnect layers arranged within one or more stacked inter-layer dielectric layers over a substrate. A bottom electrode is disposed over the one or more interconnect layers, and a top electrode is disposed over the bottom electrode. A ferroelectric layer is disposed between and contacts a first surface of the bottom electrode and a second surface of the top electrode. The ferroelectric layer includes a protrusion that extends past outer surfaces of the top electrode and the bottom electrode along a first direction that is perpendicular to a second direction that is normal to the first surface. The protrusion is confined between lines that extend along the first and second surface.
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公开(公告)号：US10727337B2
公开(公告)日：2020-07-28
申请号：US16207081
申请日：2018-11-30
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Kuo-Chi Tu , Jen-Sheng Yang , Sheng-Hung Shih , Tong-Chern Ong , Wen-Ting Chu
IPC: H01L29/78 , H01L29/51 , G11C11/22 , H01L27/1159 , H01L27/11592 , H01L29/66
Abstract: A semiconductor device includes a memory circuit and a logic circuit. The memory circuit includes a word line, a bit line, a common line and a memory transistor having a gate coupled to the word line, a drain coupled to the bit line and a source coupled to the common line. The logic circuit includes a field effect transistor (FET) having a gate, a drain and a source. The memory transistor has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a first insulating layer and a first ferroelectric (FE) material layer. The FET has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a second insulating layer and a second FE material layer.
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公开(公告)号：US10311952B2
公开(公告)日：2019-06-04
申请号：US15937257
申请日：2018-03-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chin-Chieh Yang , Chih-Yang Chang , Chang-Sheng Liao , Hsia-Wei Chen , Jen-Sheng Yang , Kuo-Chi Tu , Sheng-Hung Shih , Wen-Ting Chu , Manish Kumar Singh , Chi-Tsai Chen
Abstract: In some embodiments, the present disclosure relates to a resistive random access memory (RRAM) memory circuit. The memory circuit has a word-line decoder operably coupled to a first RRAM device and a second RRAM device by a word-line. A bit-line decoder is coupled to the first RRAM device by a first bit-line and to the second RRAM device by a second bit-line. A bias element is configured to apply a first non-zero bias voltage to the second bit-line concurrent to the bit-line decoder applying a non-zero voltage to the first bit-line.
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Patent Agency Ranking
公开(公告)号：US10249756B2
公开(公告)日：2019-04-02
申请号：US15640127
申请日：2017-06-30
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Kuo-Chi Tu , Jen-Sheng Yang , Sheng-Hung Shih , Tong-Chern Ong , Wen-Ting Chu
IPC: H01L29/78 , G11C11/22 , H01L27/1159 , H01L27/11592 , H01L29/51 , H01L29/66
Abstract: A semiconductor device includes a memory circuit and a logic circuit. The memory circuit includes a word line, a bit line, a common line and a memory transistor having a gate coupled to the word line, a drain coupled to the bit line and a source coupled to the common line. The logic circuit includes a field effect transistor (FET) having a gate, a drain and a source. The memory transistor has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a first insulating layer and a first ferroelectric (FE) material layer. The FET has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a second insulating layer and a second FE material layer.
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公开(公告)号：US10158072B1
公开(公告)日：2018-12-18
申请号：US15663671
申请日：2017-07-28
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Jen-Sheng Yang , Wen-Ting Chu , Chih-Yang Chang , Chin-Chieh Yang , Kuo-Chi Tu , Sheng-Hung Shih , Yu-Wen Liao , Hsia-Wei Chen , I-Ching Chen
IPC: H01L21/00 , H01L23/00 , H01L27/00 , H01L45/00 , H01L27/24 , H01L21/768 , H01L23/522 , H01L23/528
Abstract: A semiconductor device includes an inter-metal dielectric layer, a memory cell, a transistor and a dielectric layer. The memory cell includes a metal-insulator-metal (MIM) structure over a top surface of the inter-metal dielectric layer. The transistor underlies the inter-metal dielectric layer. The dielectric layer extends over the transistor and along the top surface of the inter-metal dielectric layer. The dielectric layer is separated from the MIM structure.
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公开(公告)号：US20180218770A1
公开(公告)日：2018-08-02
申请号：US15937257
申请日：2018-03-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chin-Chieh Yang , Chih-Yang Chang , Chang-Sheng Liao , Hsia-Wei Chen , Jen-Sheng Yang , Kuo-Chi Tu , Sheng-Hung Shih , Wen-Ting Chu , Manish Kumar Singh , Chi-Tsai Chen
CPC classification number: G11C13/004 , G11C11/1653 , G11C11/1655 , G11C11/1657 , G11C11/1673 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C2213/79 , G11C2213/82
Abstract: In some embodiments, the present disclosure relates to a resistive random access memory (RRAM) memory circuit. The memory circuit has a word-line decoder operably coupled to a first RRAM device and a second RRAM device by a word-line. A bit-line decoder is coupled to the first RRAM device by a first bit-line and to the second RRAM device by a second bit-line. A bias element is configured to apply a first non-zero bias voltage to the second bit-line concurrent to the bit-line decoder applying a non-zero voltage to the first bit-line.
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公开(公告)号：US09780302B2
公开(公告)日：2017-10-03
申请号：US15262703
申请日：2016-09-12
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hsia-Wei Chen , Wen-Ting Chu , Kuo-Chi Tu , Chih-Yang Chang , Chin-Chieh Yang , Yu-Wen Liao , Wen-Chun You , Sheng-Hung Shih
CPC classification number: H01L45/1233 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/08 , H01L45/085 , H01L45/12 , H01L45/122 , H01L45/124 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/16 , H01L45/1666 , H01L45/1683
Abstract: Some embodiments relate to an integrated circuit device. The integrated circuit device includes a resistive random access memory (RRAM) cell, which includes a top electrode and a bottom electrode that are separated by a RRAM dielectric layer. The top electrode of the RRAM cell has a recess in its upper surface. A via is disposed over the RRAM cell and contacts the top electrode within the recess.
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公开(公告)号：US20170236581A1
公开(公告)日：2017-08-17
申请号：US15425213
申请日：2017-02-06
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chin-Chieh Yang , Chih-Yang Chang , Chang-Sheng Liao , Hsia-Wei Chen , Jen-Sheng Yang , Kuo-Chi Tu , Sheng-Hung Shih , Wen-Ting Chu , Manish Kumar Singh , Chi-Tsai Chen
IPC: G11C13/00
CPC classification number: G11C13/004 , G11C11/1653 , G11C11/1655 , G11C11/1657 , G11C11/1673 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C2213/79 , G11C2213/82
Abstract: The present disclosure relates to a method and apparatus for performing a read operation of an RRAM cell, which applies a non-zero bias voltage to unselected bit-lines and select-lines to increase a read current window without damaging corresponding access transistors. In some embodiments, the method may be performed by activating a word-line coupled to a row of RRAM cells comprising a selected RRAM device by applying a first read voltage to the word-line. A second read voltage is applied to a bit-line coupled to a first electrode of the selected RRAM device. One or more non-zero bias voltages are applied to bit-lines and select-lines coupled to RRAM cells, within the row of RRAM cells, having unselected RRAM devices.
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