公开(公告)号：US20070157952A1

公开(公告)日：2007-07-12

申请号：US11724344

申请日：2007-03-15

Applicant: William Hiatt ,  Warren Farnworth ,  David Hembree ,  Peter Benson

Inventor： William Hiatt ,  Warren Farnworth ,  David Hembree ,  Peter Benson

IPC: B08B5/04 ,  B08B7/00 ,  B08B3/00

CPC classification number: B29C64/35 ,  B29C64/135 ,  B33Y30/00 ,  B33Y40/00 ,  B33Y50/02

Abstract: Methods for cleaning consolidatable material from substrates or from features that have been fabricated with the material include application of pressure, force, or a cleaning agent to the substrate or feature. The pressure, force, or cleaning agent may be applied in a variety of ways. The unconsolidated material that has been removed from the substrate or feature may also be collected, optionally filtered, and reused in a subsequent programmed material consolidation process.

Abstract translation: 从基材或由材料制成的特征清洁可固结材料的方法包括向基材或特征施加压力，力或清洁剂。 压力，力或清洁剂可以以各种方式施加。 已经从基底或特征中去除的未固结的材料也可以被收集，任选地过滤，并在随后的程序化材料固结过程中重复使用。

公开(公告)号：US20070132104A1

公开(公告)日：2007-06-14

申请号：US11701927

申请日：2007-02-02

Applicant: Warren Farnworth ,  Alan Wood ,  William Hiatt ,  James Wark ,  David Hembree ,  Kyle Kirby ,  Pete Benson

Inventor： Warren Farnworth ,  Alan Wood ,  William Hiatt ,  James Wark ,  David Hembree ,  Kyle Kirby ,  Pete Benson

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/561 ,  B33Y70/00 ,  B33Y80/00 ,  H01L21/563 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68331 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05111 ,  H01L2224/05118 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05178 ,  H01L2224/0518 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05559 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13009 ,  H01L2224/13024 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2225/06596 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/18161 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/351 ,  H01L2924/207 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

Abstract: A semiconductor component includes a base die and a secondary die stacked on and bonded to the base die. The base die includes conductive vias which form an internal signal transmission system for the component, and allow the circuit side of the secondary die to be bonded to the back side of the base die. The component also includes an array of terminal contacts on the circuit side of the base die in electrical communication with the conductive vias. The component can also include an encapsulant on the back side of the base die, which substantially encapsulates the secondary die, and a polymer layer on the circuit side of the base die which functions as a protective layer, a rigidifying member and a stencil for forming the terminal contacts. A method for fabricating the component includes the step of bonding singulated secondary dice to base dice on a base wafer, or bonding a secondary wafer to the base wafer, or bonding singulated secondary dice to singulated base dice.

Abstract translation: 半导体部件包括基模和层叠在基模上的二次模。 基模具包括形成用于部件的内部信号传输系统的导电通孔，并允许二次管芯的电路侧接合到基座的后侧。 该组件还包括与导电通孔电连通的基座芯片的电路侧上的端子触点阵列。 该组件还可以包括在基模的背侧上的密封剂，其基本上封装次模，以及在用作保护层的基模的电路侧上的聚合物层，用于形成的用于固化的模板 终端接触。 一种用于制造该部件的方法包括将单个二次骰子接合到基底晶片上的基底骰子上，或将次晶片接合到基底晶片，或将单个二次骰子接合到单个基体骰子的步骤。

公开(公告)号：US20070045632A1

公开(公告)日：2007-03-01

申请号：US11217877

申请日：2005-09-01

Applicant: Steven Oliver ,  Lu Velicky ,  William Hiatt ,  David Hembree ,  Mark Tuttle ,  Sidney Rigg ,  James Wark ,  Warren Farnworth ,  Kyle Kirby

Inventor： Steven Oliver ,  Lu Velicky ,  William Hiatt ,  David Hembree ,  Mark Tuttle ,  Sidney Rigg ,  James Wark ,  Warren Farnworth ,  Kyle Kirby

IPC: H01L33/00

CPC classification number: H01L21/00 ,  H01L21/76898 ,  H01L23/552 ,  H01L27/14609 ,  H01L27/14618 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/14685 ,  H01L27/14687 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Microelectronic imaging units and methods for manufacturing a plurality of imaging units at the wafer level are disclosed herein. In one embodiment, a method for manufacturing a plurality of imaging units includes providing an imager workpiece having a plurality of imaging dies including integrated circuits, external contacts electrically coupled to the integrated circuits, and image sensors operably coupled to the integrated circuits. The individual image sensors include at least one dark current pixel at a perimeter portion of the image sensor. The method includes depositing a cover layer onto the workpiece and over the image sensors. The method further includes patterning and selectively developing the cover layer to form discrete volumes of cover layer material over corresponding image sensors. The discrete volumes of cover layer material have sidewalls aligned with an inboard edge of the individual dark current pixels such that the dark current pixels are not covered by the discrete volumes.

Abstract translation: 本文公开了用于在晶片级制造多个成像单元的微电子成像单元和方法。 在一个实施例中，制造多个成像单元的方法包括提供具有多个成像管芯的成像工件，所述成像管芯包括集成电路，电耦合到集成电路的外部触点以及可操作地耦合到集成电路的图像传感器。 各个图像传感器包括在图像传感器的周边部分处的至少一个暗电流像素。 该方法包括将覆盖层沉积在工件上并在图像传感器上方。 该方法还包括图案化和选择性地显影覆盖层以在对应的图像传感器上形成分离体积的覆盖层材料。 覆盖层材料的离散体积具有与各个暗电流像素的内侧边缘对准的侧壁，使得暗电流像素不被离散体积覆盖。

公开(公告)号：US20070001293A1

公开(公告)日：2007-01-04

申请号：US11516243

申请日：2006-09-06

Applicant: Tongbi Jiang ,  Li Li ,  William Hiatt

Inventor： Tongbi Jiang ,  Li Li ,  William Hiatt

IPC: H01L23/34

CPC classification number: H01L21/486 ,  H01L21/4803 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/49816 ,  H01L24/10 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81801 ,  H01L2224/83005 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/0032 ,  H05K3/0052 ,  H05K3/0058 ,  H05K3/4644 ,  H05K3/4682 ,  H05K2203/016 ,  H05K2203/0384 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: Methods for creating redistribution layers for only selected dice, such as known good dice, to form relatively thin semiconductor component assemblies and packages, and the assemblies and packages created by the methods, are disclosed. A sacrificial layer is deposited on a support substrate. An etch stop layer having a lower etch is deposited on the sacrificial layer. Redistribution lines in a dielectric material are formed on the support substrate on the etch stop layer. Semiconductor dice, either singulated or at the wafer level, are connected to the redistribution lines. The assembly may be scribed to allow the sacrificial layer to be etched to enable removal of the semiconductor dice and associated redistribution layer from the support substrate. The etch stop layer is removed to allow access to the redistribution lines for conductive bumping.

Abstract translation: 公开了用于仅为所选择的骰子创建再分布层（例如已知的骰子）以形成相对薄的半导体元件组件和封装以及由该方法产生的组件和封装件的方法。 牺牲层沉积在支撑衬底上。 具有较低蚀刻的蚀刻停止层沉积在牺牲层上。 介电材料中的再分布线形成在蚀刻停止层上的支撑衬底上。 单片化或晶圆级的半导体管芯连接到再分配线。 可以对组件进行划线以允许蚀刻牺牲层，以便能够从支撑衬底去除半导体晶片和相关联的再分配层。 去除蚀刻停止层以允许进入用于导电凸起的再分配线。

公开(公告)号：US20060261446A1

公开(公告)日：2006-11-23

申请号：US11133085

申请日：2005-05-19

Applicant: Alan Wood ,  William Hiatt ,  David Hembree

Inventor： Alan Wood ,  William Hiatt ,  David Hembree

IPC: H01L23/48 ,  H01L21/44

CPC classification number: H01L21/76898 ,  H01L21/4885 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/4951 ,  H01L23/4985 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/50 ,  H01L24/78 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/86 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06102 ,  H01L2224/06136 ,  H01L2224/11003 ,  H01L2224/1131 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/114 ,  H01L2224/1147 ,  H01L2224/116 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/2518 ,  H01L2224/45015 ,  H01L2224/451 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/4824 ,  H01L2224/4845 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/48799 ,  H01L2224/78301 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/85001 ,  H01L2224/851 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/19042 ,  Y10T29/53187 ,  Y10T29/53209 ,  H01L2924/00 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2224/83851 ,  H01L2224/05552

Abstract: A backside method for fabricating a semiconductor component with a conductive interconnect includes the step of providing a semiconductor substrate having a circuit side, a backside, and a substrate contact on the circuit side. The method also includes the steps of forming a substrate opening from the backside to the substrate contact, and then bonding the conductive interconnect to an inner surface of the substrate contact. A system for performing the method includes the semiconductor substrate, a thinning system for thinning the semiconductor substrate, an etching system for forming the substrate opening, and a bonding system for bonding the conductive interconnect to the substrate contact. The semiconductor component can be used to form module components, underfilled components, stacked components, and image sensor semiconductor components.

Abstract translation: 用于制造具有导电互连的半导体部件的背面方法包括在电路侧提供具有电路侧，背面和基板接触的半导体衬底的步骤。 该方法还包括以下步骤：从背面形成衬底开口到衬底触点，然后将导电互连件接合到衬底触点的内表面。 用于执行该方法的系统包括半导体衬底，用于使半导体衬底变薄的变薄系统，用于形成衬底开口的蚀刻系统，以及用于将导电互连件接合到衬底接触件的接合系统。 半导体元件可用于形成模块组件，底部填充组件，堆叠组件和图像传感器半导体组件。

公开(公告)号：US20060244475A1

公开(公告)日：2006-11-02

申请号：US11477217

申请日：2006-06-29

Applicant: Kyle Kirby ,  Warren Farnworth ,  James Wark ,  William Hiatt ,  David Hembree ,  Alan Wood

Inventor： Kyle Kirby ,  Warren Farnworth ,  James Wark ,  William Hiatt ,  David Hembree ,  Alan Wood

IPC: G01R31/26

CPC classification number: G01R1/0735 ,  G01R1/07314 ,  H01L23/13 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01R12/714 ,  H01R13/24 ,  H01R2201/20 ,  H05K3/326 ,  H05K7/1069 ,  H05K2201/0314 ,  H05K2201/09036 ,  H05K2201/10378 ,  Y10T29/49165 ,  Y10T29/49174 ,  Y10T29/49204 ,  Y10T29/49222 ,  H01L2224/05599

Abstract: A compliant contact pin assembly and a contactor card and methods for testing therewith are provided. The compliant contact pin assembly includes a contact pin formed from a portion of a substrate with the contact pin compliantly held suspended within the substrate by a compliant coupling structure. The suspension within the substrate results in a compliant deflection orthogonal to the plane of the substrate. The contact pin assembly is formed by generally thinning the substrate around the contact pin location and then specifically thinning the substrate immediately around the contact pin location for forming a void. The contact pin is compliantly coupled, in one embodiment by compliant coupling material, and in another embodiment by compliantly flexible portions of the substrate.

Abstract translation: 提供了一种柔性接触销组件和接触器卡以及用于测试的方法。 柔性接触销组件包括由基板的一部分形成的接触销，其中触头销顺从地保持通过柔性联接结构悬挂在基板内。 衬底内的悬浮液导致与衬底的平面垂直的柔顺偏转。 接触销组件通过使基板围绕接触销位置大体变薄而形成，然后特别地使基板在接触销位置周围特别地变薄以形成空隙。 在一个实施例中，接触销被顺从地联接，在一个实施例中通过柔性耦合材料，并且在另一个实施例中，通过柔性柔性部分的衬底。

公开(公告)号：US20060199363A1

公开(公告)日：2006-09-07

申请号：US11416824

申请日：2006-05-03

Applicant: Kyle Kirby ,  Salman Akram ,  David Hembree ,  Sidney Rigg ,  Warren Farnworth ,  William Hiatt

Inventor： Kyle Kirby ,  Salman Akram ,  David Hembree ,  Sidney Rigg ,  Warren Farnworth ,  William Hiatt

IPC: H01L21/44

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K1/0306 ,  H05K3/4038 ,  H05K3/422 ,  H05K3/423 ,  H05K2201/0305 ,  H05K2201/09827 ,  H05K2203/072 ,  H05K2203/1147 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Microelectronic devices, methods for packaging microelectronic devices, and methods for forming interconnects in microelectronic devices are disclosed herein. In one embodiment, a method comprises providing a microelectronic substrate having a front side and a backside. The substrate has a microelectronic die including an integrated circuit and a terminal operatively coupled to the integrated circuit. The method also includes forming a passage at least partially through the substrate and having an opening at the front side and/or backside of the substrate. The method further includes sealing the opening with a conductive cap that closes one end of the passage while another end of the passage remains open. The method then includes filling the passage with a conductive material.

公开(公告)号：US20060191882A1

公开(公告)日：2006-08-31

申请号：US11414999

申请日：2006-05-01

Applicant: Charles Watkins ,  William Hiatt

Inventor： Charles Watkins ,  William Hiatt

IPC: B23K26/38

CPC classification number: B23K26/382 ,  B23K26/03 ,  B23K26/0342 ,  B23K26/361 ,  B23K26/362 ,  B23K26/38 ,  B23K26/40 ,  B23K2101/40 ,  B23K2103/50 ,  B23K2103/56 ,  H01L21/486 ,  H01L21/76898 ,  H05K3/0026 ,  H05K2203/163 ,  Y10T29/49165

Abstract: Systems and methods for forming apertures in microfeature workpieces are disclosed herein. In one embodiment, a method includes directing a laser beam toward a microfeature workpiece to form an aperture and sensing the laser beam pass through the microfeature workpiece in real time. The method can further include determining a number of pulses of the laser beam and/or an elapsed time to form the aperture and controlling the laser beam based on the determined number of pulses and/or the determined elapsed time to form a second aperture in the microfeature workpiece.

公开(公告)号：US20060081966A1

公开(公告)日：2006-04-20

申请号：US11281631

申请日：2005-11-17

Applicant: Warren Farnworth ,  Kyle Kirby ,  William Hiatt

Inventor： Warren Farnworth ,  Kyle Kirby ,  William Hiatt

IPC: H01L23/58

CPC classification number: H01L21/463 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3185 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2224/03

Abstract: Improved chip-scale packages wherein semiconductor die side surfaces are free of the material defects associated with prior art chip-scale package formation. In one embodiment, chip-scale package includes a semiconductor die includes an active surface, an opposing passive surface, and a plurality of etched side surfaces extending from the active surface to the passive surface. A first protective coating may extend over the active surface of the semiconductor die and a second protective coating may extend over the passive surface of the semiconductor die wherein one of the first protective coating and the second protective coating extends over the plurality of etched side surfaces of the semiconductor die.

Abstract translation: 改进的芯片级封装，其中半导体管芯侧表面没有与现有技术的芯片级封装形成相关的材料缺陷。 在一个实施例中，芯片级封装包括半导体管芯，其包括有源表面，相对的被动表面以及从活性表面延伸到被动表面的多个蚀刻侧表面。 第一保护涂层可以在半导体管芯的有效表面上延伸，并且第二保护涂层可以在半导体管芯的钝化表面上延伸，其中第一保护涂层和第二保护涂层中的一个在多个蚀刻的侧表面上延伸 半导体芯片。

公开(公告)号：US20060046088A1

公开(公告)日：2006-03-02

申请号：US10934635

申请日：2004-09-02

Applicant: Salman Akram ,  James Wark ,  William Hiatt

Inventor： Salman Akram ,  James Wark ,  William Hiatt

IPC: H01L29/12

CPC classification number: H01L21/76879 ,  C23C18/1607 ,  C23C18/1637 ,  C23C18/1831 ,  C23C18/1834 ,  C23C18/34 ,  C23C18/36 ,  H01L21/288 ,  H01L21/76898 ,  H01L2924/00013 ,  Y10T428/12528 ,  Y10T428/24917 ,  H01L2224/29099

Abstract: A method of selectively plating nickel on an intermediate semiconductor device structure. The method comprises providing an intermediate semiconductor device structure having at least one aluminum or copper structure and at least one tungsten structure. One of the aluminum or copper structure and the tungsten structure is nickel plated while the other remains unplated. The aluminum or copper structure or the tungsten structure may first be activated toward nickel plating. The activated aluminum or copper structure or the activated tungsten structure may then be nickel plated by immersing the intermediate semiconductor device structure in an electroless nickel plating solution. The unplated aluminum or copper structure or the unplated tungsten structure may subsequently be nickel plated by activating the unplated structure and nickel plating the activated structure. A method of simultaneously plating the aluminum or copper structure and the tungsten structure with nickel is also disclosed, as is an intermediate semiconductor device structure.

Abstract translation: 在中间半导体器件结构上选择性镀镍的方法。 该方法包括提供具有至少一个铝或铜结构和至少一个钨结构的中间半导体器件结构。 铝或铜结构之一和钨结构是镀镍的，而另一个保持未镀层。 可以首先将铝或铜结构或钨结构活化成镀镍。 然后可以通过将中间半导体器件结构浸入无电镀镍溶液中来将活化的铝或铜结构或活化的钨结构镀镍。 然后通过激活未镀层的结构和镀镍活化的结构，可以将未镀覆的铝或铜结构或未镀覆的钨结构镀镍。 还公开了一种用镍同时电镀铝或铜结构和钨结构的方法，以及中间半导体器件结构。