公开(公告)号：US20050101158A1

公开(公告)日：2005-05-12

申请号：US11012569

申请日：2004-12-15

Applicant: Warren Farnworth ,  Warren Farnworth

Inventor： Warren Farnworth ,  Warren Farnworth

IPC: H01L23/31 ,  H01L21/44 ,  H01L21/31 ,  H01L21/469

CPC classification number: H01L21/44 ,  B33Y10/00 ,  B33Y30/00 ,  B33Y40/00 ,  B33Y80/00 ,  H01L23/3157 ,  H01L23/3192 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2224/29099 ,  H01L2924/00

Abstract: Methods for forming protective layers on semiconductor devices, including semiconductor devices that are carried by fabrication substrates, that are parts of assemblies, and that include individual dies, includes at least partially consolidating previously unconsolidated material selectively, in accordance with a program. The method may include use of a machine vision system or other object recognition apparatus to provide precise die-specific alignment. A protective structure may be formed to include at least one layer or segment of dielectric material having a controlled thickness or depth and a precise boundary. The layer or segment may include precisely sized, shaped, and located apertures through which conductive terminals, such as bond pads, on the surface of the die may be accessed. Dielectric material may also be employed as a structure to mechanically reinforce a die-to-substrate (e.g., die-to-lead frame) attachment.

Abstract translation: 在半导体器件上形成保护层的方法，包括由制造衬底承载的半导体器件，其是组件的部件，并且包括单独的裸片，包括根据程序选择性地至少部分地固结先前未合并的材料。 该方法可以包括使用机器视觉系统或其他物体识别装置来提供精确的模具特异性对准。 可以形成保护结构以包括具有受控厚度或深度和精确边界的至少一个介电材料层或段。 层或段可以包括精确尺寸的，成形的和定位的孔，通过该孔可以访问管芯表面上的导电端子，例如接合焊盘。 电介质材料也可以用作结构以机械加强芯片到基板（例如，管芯到引线框架）的连接。

公开(公告)号：US20110233777A1

公开(公告)日：2011-09-29

申请号：US13154550

申请日：2011-06-07

Applicant: Salman Akram ,  Charles Watkins ,  Mark Hiatt ,  David Hembree ,  James Wark ,  Warren Farnworth ,  Mark Tuttle ,  Sidney Rigg ,  Steven Oliver ,  Kyle Kirby ,  Alan Wood ,  Lu Velicky

Inventor： Salman Akram ,  Charles Watkins ,  Mark Hiatt ,  David Hembree ,  James Wark ,  Warren Farnworth ,  Mark Tuttle ,  Sidney Rigg ,  Steven Oliver ,  Kyle Kirby ,  Alan Wood ,  Lu Velicky

IPC: H01L23/498 ,  H01L23/48

CPC classification number: H01L21/76877 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/45 ,  H01L27/14634 ,  H01L27/14636 ,  H01L2221/6834 ,  H01L2224/02166 ,  H01L2224/0554 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.

Abstract translation: 公开了一种用于成像器，存储器和其他集成电路应用的透晶片互连，从而消除了对引线接合的需要，使得结合这种互连的器件可堆叠并且实现成像器件的晶片级封装。 此外，实现了更小且更可靠的管芯封装，并且由于信号路径长度的减小，电路寄生（例如，L和R）被减小。

公开(公告)号：US07768040B2

公开(公告)日：2010-08-03

申请号：US11551899

申请日：2006-10-23

Applicant: Warren Farnworth

Inventor： Warren Farnworth

IPC: H01L27/146

CPC classification number: H01L31/0232 ,  H01L27/14618 ,  H01L27/14683 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014

Abstract: An imager device is disclosed including a first substrate having an array of photo-sensitive elements formed thereon, a first conductive layer formed above the first substrate, a first conductive member extending through the first substrate, the first conductive member being conductively coupled to the first conductive layer, a standoff structure formed above the first substrate, a second conductive layer formed above the standoff structure, the second conductive layer being conductively coupled to the first conductive layer, and an electrically powered device positioned above the standoff structure, the electrically powered device being electrically coupled to the second conductive layer. A method of making an imager device is disclosed including providing a first substrate having a first conductive layer and an array of photosensitive elements formed above the first substrate, forming a conductive member that extends through the first substrate and is conductively coupled to the first conductive layer, forming a standoff structure above the first substrate, forming a patterned conductive layer above the standoff structure, the patterned conductive layer being conductively coupled to the first conductive layer, and conductively coupling an electrically powered device to the patterned conductive layer positioned above the standoff structure.

Abstract translation: 公开了一种成像器件，其包括具有形成在其上的感光元件阵列的第一衬底，形成在第一衬底上方的第一导电层，延伸穿过第一衬底的第一导电构件，第一导电构件导电耦合到第一衬底 导电层，形成在第一基板上方的间隔结构，形成在支架结构上方的第二导电层，第二导电层导电耦合到第一导电层，以及位于支架结构之上的电动设备，电动设备 电耦合到第二导电层。 公开了一种制造成像器件的方法，包括提供具有第一导电层的第一衬底和形成在第一衬底上方的感光元件阵列的第一衬底，形成延伸穿过第一衬底的导电构件并与第一导电层 ，在所述第一基板上形成间隔结构，在所述支座结构之上形成图案化导电层，所述图案化导电层导电耦合到所述第一导电层，并且将电动装置导电地连接到位于所述支架结构之上的图案化导电层 。

公开(公告)号：US07470563B2

公开(公告)日：2008-12-30

申请号：US11248914

申请日：2005-10-11

Applicant: William Mark Hiatt ,  Warren Farnworth

Inventor： William Mark Hiatt ,  Warren Farnworth

IPC: H01L21/00

CPC classification number: H01L23/3114 ,  H01L21/563 ,  H01L23/3107 ,  H01L23/3157 ,  H01L23/467 ,  H01L23/473 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/10126 ,  H01L2224/13022 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83102 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A microelectronic package and method for forming such a package. In one embodiment, the package can include a microelectronic substrate having first connection sites, and a support member having second connection sites and third connection sites, with the third connection sites accessible for electrical coupling to other electrical structures. A plurality of electrically conductive couplers are connected between the first connection sites and the second connection sites, with neighboring conductive couplers being spaced apart to define at least one flow channel. The at least one flow channel is in fluid communication with a region external to the microelectronic substrate. The generally non-conductive material can be spaced apart from the support member to allow the microelectronic substrate to be separated from the support member.

Abstract translation: 一种用于形成这种封装的微电子封装和方法。 在一个实施例中，封装可以包括具有第一连接位置的微电子衬底和具有第二连接位置和第三连接位置的支撑构件，其中第三连接位置可用于电耦合到其它电气结构。 多个导电耦合器连接在第一连接位置和第二连接位置之间，其中相邻的导电耦合器间隔开以限定至少一个流动通道。 至少一个流动通道与微电子衬底外部的区域流体连通。 通常非导电材料可以与支撑构件间隔开，以允许微电子衬底与支撑构件分离。

公开(公告)号：US20080212303A1

公开(公告)日：2008-09-04

申请号：US11681340

申请日：2007-03-02

Applicant: Warren Farnworth ,  Ross Dando

Inventor： Warren Farnworth ,  Ross Dando

IPC: H05K9/00

CPC classification number: H05K9/0043 ,  G06K19/07327

Abstract: A device that is adapted to receive a card including information, such as confidential information, in machine-readable form is disclosed. The device includes a body, wherein at least a portion of the body is made of a material that is adapted to attenuate or disrupt an interrogating signal sent toward the card or a return signal sent from the card to thereby at least reduce the likelihood that the confidential information is read from the card.

Abstract translation: 公开了一种适于以机器可读形式接收包括诸如机密信息等信息的卡的设备。 该装置包括主体，其中主体的至少一部分由适于衰减或破坏朝向卡发送的询问信号的材料或从卡发送的返回信号，从而至少降低了可能性 从卡中读取机密信息。

公开(公告)号：US20080111574A1

公开(公告)日：2008-05-15

申请号：US12017262

申请日：2008-01-21

Applicant: Warren Farnworth ,  William Waller ,  Leland Nevill ,  Raymond Beffa ,  Eugene Cloud

Inventor： Warren Farnworth ,  William Waller ,  Leland Nevill ,  Raymond Beffa ,  Eugene Cloud

IPC: G01R31/02

CPC classification number: G01R31/025 ,  G01R31/2884

Abstract: A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.

Abstract translation: 用于将形成在半导体晶片的表面上的短路集成电路（IC）与形成在晶片上的与短路IC互连的其他IC隔离的电路包括用于感测短路IC的短路IC内的控制电路 电路。 控制电路可以以各种方式感测短路，包括感测由短路IC吸引的过电流，以及感测短路IC内的异常低或高电压。 短路IC内的开关电路响应于控制电路感测短路而选择性地将短路IC与晶片上的其它IC隔离。 结果，如果晶片处于探针测试之下，例如，在短路IC隔离的同时，其它IC上的测试可以不中断地继续。

公开(公告)号：US20080031032A1

公开(公告)日：2008-02-07

申请号：US11905823

申请日：2007-10-04

Applicant: Warren Farnworth

Inventor： Warren Farnworth

IPC: G11C11/00

CPC classification number: G11C13/003 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/72 ,  G11C2213/76 ,  G11C2213/79

Abstract: A circuit and method for writing to a variable resistance memory cell. The circuit includes a variable resistance memory cell, a switchable current blocking device and a charge storing element. As the switchable current blocking device blocks current flow through the variable resistance memory cell, the charge storing element charges. When the switchable current blocking device is not blocking current, the charge storing element discharges through the variable resistance memory cell, generating a write current sufficient to write high resistance variable resistance memory cells.

Abstract translation: 一种用于写入可变电阻存储单元的电路和方法。 电路包括可变电阻存储单元，可切换电流阻断装置和电荷存储元件。 由于可切换电流阻断装置阻塞通过可变电阻存储单元的电流，所以电荷存储元件充电。 当可切换电流阻断装置不阻塞电流时，电荷存储元件通过可变电阻存储单元放电，产生足以写入高电阻可变电阻存储单元的写入电流。

公开(公告)号：US20080001068A1

公开(公告)日：2008-01-03

申请号：US11898291

申请日：2007-09-11

Applicant: Warren Farnworth ,  Alan Wood

Inventor： Warren Farnworth ,  Alan Wood

IPC: H01L27/14

CPC classification number: H01L27/14687 ,  H01L27/14618 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/14685 ,  H01L31/0232 ,  H01L2224/13

Abstract: Microelectronic imaging devices and associated methods for attaching transmissive elements are disclosed. A manufacturing method in accordance with one embodiment of the invention includes providing an imager workpiece having multiple image sensor dies configured to detect energy over a target frequency. The image sensor dies can include an image sensor and a corresponding lens device positioned proximate to the image sensor. The method can further include positioning standoffs adjacent to the lens devices while the image sensor dies are connected to each other via the imager workpiece. At least one transmissive element can be attached to the workpiece at least proximate to the standoffs so the lens devices are positioned between the corresponding image sensors and the at least one transmissive element. Accordingly, the at least one transmissive element can protect the image sensors while the image sensor dies are still connected. In a subsequent process, the image sensor dies can be separated from each other.

Abstract translation: 公开了用于附接透射元件的微电子成像装置和相关方法。 根据本发明的一个实施例的制造方法包括提供具有多个图像传感器管芯的成像器工件，所述图像传感器管被配置为检测目标频率上的能量。 图像传感器管芯可以包括图像传感器和位于图像传感器附近的对应的透镜装置。 该方法还可以包括在图像传感器管芯经由成像器工件相互连接的同时定位与透镜设备相邻的间隔。 至少一个透射元件可以至少靠近支座附接到工件，使得透镜装置位于相应的图像传感器和至少一个透射元件之间。 因此，至少一个透射元件可以在图像传感器管芯仍然连接的同时保护图像传感器。 在随后的过程中，图像传感器管芯可以彼此分离。

公开(公告)号：US20070262464A1

公开(公告)日：2007-11-15

申请号：US11781083

申请日：2007-07-20

Applicant: Charles Watkins ,  Kyle Kirby ,  Alan Wood ,  Salman Akram ,  Warren Farnworth

Inventor： Charles Watkins ,  Kyle Kirby ,  Alan Wood ,  Salman Akram ,  Warren Farnworth

IPC: H01L21/302 ,  H01L23/48 ,  H01L21/461 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/76898

Abstract: Methods for forming through vias in a semiconductor substrate and resulting structures are disclosed. In one embodiment, a through via may be formed by forming a partial via from the active surface through a conductive element thereon and a portion of the substrate underlying the conductive element. The through via may then be completed by laser ablation or drilling from the back surface. In another embodiment, a partial via may be formed by laser ablation or drilling from the back surface of a substrate to a predetermined distance therein. The through via may be completed from the active surface by forming a partial via extending through the conductive element and the underlying substrate to intersect the laser-drilled partial via. In another embodiment, a partial via may first be formed by laser ablation or drilling from the back surface of the substrate followed by dry etching to complete the through via.

Abstract translation: 公开了在半导体衬底中形成贯通孔的方法和所得到的结构。 在一个实施例中，通孔可以通过从其上的导电元件和导电元件下面的基底的一部分从活性表面形成部分通孔来形成通孔。 然后可以通过从后表面的激光烧蚀或钻孔来完成通孔。 在另一个实施例中，部分通孔可以通过激光烧蚀或从衬底的背面钻孔到其中的预定距离来形成。 通孔可以通过形成延伸通过导电元件和下面的衬底以与激光钻孔的部分通孔相交的部分通孔从活性表面完成。 在另一个实施例中，可以首先通过激光烧蚀或从衬底的背面进行钻孔形成部分通孔，然后通过干蚀刻来完成通孔。

公开(公告)号：US20070179655A1

公开(公告)日：2007-08-02

申请号：US11731874

申请日：2007-03-30

Applicant: Warren Farnworth

Inventor： Warren Farnworth

IPC: G06F19/00

CPC classification number: B29C64/35 ,  B29C64/135 ,  B33Y30/00 ,  B33Y40/00 ,  B33Y50/02

Abstract: A programmed material consolidation apparatus includes at least one fabrication site and a material consolidation system associated with the at least one fabrication site. The at least one fabrication site may be configured to receive one or more fabrication substrates, such as semiconductor substrates. A machine vision system with a translatable or locationally fixed camera may be associated with the at least one fabrication site and the material consolidation system. A cleaning component may also be associated with the at least one fabrication site. The cleaning component may share one or more elements with the at least one fabrication site, or may be separate therefrom. The programmed material consolidation apparatus may also include a substrate handling system, which places fabrication substrates at appropriate locations of the programmed material consolidation apparatus.

Abstract translation: 编程材料合并装置包括与所述至少一个制造位置相关联的至少一个制造位置和材料固结系统。 至少一个制造位置可以被配置为接收一个或多个制造衬底，例如半导体衬底。 具有可移动或位置固定的照相机的机器视觉系统可以与至少一个制造场所和材料合并系统相关联。 清洁部件也可以与至少一个制造部位相关联。 清洁部件可以与至少一个制造部位共享一个或多个元件，或者可以与其分开。 编程材料合并装置还可以包括基板处理系统，其将制造基板放置在编程材料固结装置的适当位置。