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    Microfeature workpieces and methods for forming interconnects in microfeature workpieces
    2.
    发明申请
    Microfeature workpieces and methods for forming interconnects in microfeature workpieces 有权
    微型工件和在微型工件中形成互连的方法

    公开(公告)号：US20070045858A1

    公开(公告)日：2007-03-01

    申请号：US11218243

    申请日：2005-09-01

    Applicant: Kyle Kirby ,  William Hiatt ,  Richard Stocks

    Inventor： Kyle Kirby ,  William Hiatt ,  Richard Stocks

    IPC: H01L21/4763 ,  H01L23/48

    CPC classification number: H01L21/76898 ,  H01L21/76868 ,  H01L21/76873 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

    Abstract: Methods for forming interconnects in microfeature workpieces, and microfeature workpieces having such interconnects are disclosed herein. In one embodiment, a method of forming an interconnect in a microfeature workpiece includes forming a hole extending through a terminal and a dielectric layer to at least an intermediate depth in a substrate of a workpiece. The hole has a first lateral dimension in the dielectric layer and a second lateral dimension in the substrate proximate to an interface between the dielectric layer and the substrate. The second lateral dimension is greater than the first lateral dimension. The method further includes constructing an electrically conductive interconnect in at least a portion of the hole and in electrical contact with the terminal.

    Abstract translation: 在微型工件中形成互连的方法以及具有这种互连的微型工件在此公开。 在一个实施例中，在微特征工件中形成互连的方法包括：将通过端子和电介质层延伸的孔形成在工件的衬底中的至少中间深度。 该孔在电介质层中具有第一横向尺寸，并且该基板中的第二横向尺寸靠近介电层和基底之间的界面。 第二横向尺寸大于第一横向尺寸。 该方法还包括在孔的至少一部分中与端子电接触地构造导电互连。

    Systems and methods for testing microelectronic imagers and microfeature devices
    4.
    发明申请
    Systems and methods for testing microelectronic imagers and microfeature devices 有权
    用于测试微电子成像器和微特征器件的系统和方法

    公开(公告)号：US20060255826A1

    公开(公告)日：2006-11-16

    申请号：US11409060

    申请日：2006-04-24

    Applicant: Salman Akram ,  William Hiatt ,  Alan Wood ,  Charles Watkins ,  Kyle Kirby

    Inventor： Salman Akram ,  William Hiatt ,  Alan Wood ,  Charles Watkins ,  Kyle Kirby

    IPC: G01R31/26

    CPC classification number: G01R31/2635 ,  G01R31/2831

    Abstract: Systems and methods for testing microelectronic imagers and microfeature devices are disclosed herein. In one embodiment, a method includes providing a microfeature workpiece including a substrate having a front side, a backside, and a plurality of microelectronic dies. The individual dies include an integrated circuit and a plurality of contact pads at the backside of the substrate operatively coupled to the integrated circuit. The method includes contacting individual contact pads with corresponding pins of a probe card. The method further includes testing the dies. In another embodiment, the individual dies can further comprise an image sensor at the front side of the substrate and operatively coupled to the integrated circuit. The image sensors are illuminated while the dies are tested.

    Abstract translation: 本文公开了用于测试微电子成像器和微特征器件的系统和方法。 在一个实施例中，一种方法包括提供微功能工件，其包括具有正面，背面和多个微电子管芯的衬底。 各个管芯包括集成电路和在衬底的背面可操作地耦合到集成电路的多个接触焊盘。 该方法包括使各个接触垫与探针卡的相应引脚接触。 该方法还包括测试模具。 在另一个实施例中，各个管芯还可以包括在衬底的前侧的图像传感器，并可操作地耦合到集成电路。 在测试模具时，图像传感器被照亮。

    Programmed material consolidation processes for fabricating electrical contacts and the resulting electrical contacts
    6.
    发明申请
    Programmed material consolidation processes for fabricating electrical contacts and the resulting electrical contacts 审中-公开
    用于制造电触点和由此产生的电触头的程序化材料固结工艺

    公开(公告)号：US20060211313A1

    公开(公告)日：2006-09-21

    申请号：US11429012

    申请日：2006-05-04

    Applicant: Warren Farnworth ,  William Hiatt ,  Charles Watkins

    Inventor： Warren Farnworth ,  William Hiatt ,  Charles Watkins

    IPC: H01R13/02

    CPC classification number: H01R13/02 ,  B33Y30/00 ,  B33Y80/00 ,  H01R13/2414 ,  H01R2201/20

    Abstract: An electrical contact for use with a semiconductor device, a carrier, a probe card, or another substrate includes a dielectric core, a conductive coating on at least a portion of the core, or both that are at least partially fabricated by a programmed material consolidation process, such as, but not limited to, stereolithography, in which unconsolidated material is selectively consolidated in accordance with a program. The electrical contact may be flexible and resilient or it may be rigid. Protective structures may accompany flexible, resilient contacts to prevent deformation thereof beyond their elastic limits.

    Abstract translation: 与半导体器件，载体，探针卡或另一基底一起使用的电触点包括介电芯，芯的至少一部分上的导电涂层或两者，至少部分地由编程材料固结 方法，例如但不限于立体光刻术，其中根据程序选择性地固结未固结的材料。 电接触可以是柔性的和弹性的，或者它可以是刚性的。 保护结构可以伴随柔性弹性触点，以防止其变形超出其弹性极限。

    Methods for fabricating electronic device components that include protruding contacts and electronic device components so fabricated
    7.
    发明申请
    Methods for fabricating electronic device components that include protruding contacts and electronic device components so fabricated 审中-公开
    用于制造包括突出接触件和如此制造的电子器件部件的电子器件部件的方法

    公开(公告)号：US20060205291A1

    公开(公告)日：2006-09-14

    申请号：US11429011

    申请日：2006-05-04

    Applicant: Warren Farnworth ,  William Hiatt ,  Charles Watkins

    Inventor： Warren Farnworth ,  William Hiatt ,  Charles Watkins

    IPC: H01R13/02

    CPC classification number: H01R13/02 ,  B33Y30/00 ,  B33Y80/00 ,  H01R13/2414 ,  H01R2201/20

    Abstract: A method for fabricating a semiconductor device component, such as a probe card, includes providing a support plate with at least one aperture therethrough and providing at least one contact in the at least one aperture. Ends of the at least one contact may be enlarged to retain the same within the at least one aperture. A protective structure may be provided to prevent excessive compression of the at least one contact. The support plate, all or part of the at least one contact, the protective structure, or a combination thereof may be formed by a programmed material consolidation process, such as stereolithography, in which unconsolidated material is selectively consolidated in accordance with a program.

    Abstract translation: 用于制造诸如探针卡的半导体器件部件的方法包括提供具有穿过其中的至少一个孔的支撑板，并在所述至少一个孔中提供至少一个触点。 可以扩大至少一个触点的端部以将其保持在至少一个孔内。 可以提供保护结构以防止至少一个接触件的过度压缩。 支撑板，全部或部分至少一个触点，保护结构或其组合可以通过程序化材料固结工艺（例如立体光刻）形成，其中根据程序选择性地固结未固结的材料。

    Through-hole conductors for semiconductor substrates and method for making same
    10.
    发明申请
    Through-hole conductors for semiconductor substrates and method for making same 失效
    用于半导体衬底的通孔导体及其制造方法

    公开(公告)号：US20060040494A1

    公开(公告)日：2006-02-23

    申请号：US11256791

    申请日：2005-10-24

    Applicant: William Hiatt

    Inventor： William Hiatt

    IPC: H01L21/44

    CPC classification number: H01L21/288 ,  H01L21/2885 ,  H01L21/76898

    Abstract: A method, structure and system for forming a through-hole conductor in a substrate includes forming a hole having an inner surface from a first side of the semiconductor substrate to a second side of the semiconductor substrate and plating the inner surface of the semiconductor substrate to form a conductive element when a plating solution is forced from the first side of the semiconductor substrate to the second side of the semiconductor substrate through the hole. The hole is plated in a generally planar plating topology from the first side to the second side of the semiconductor wafer. The through-hole conductor may be formed in a plating system where the semiconductor substrate forms at least a partial partition between a higher pressure bath and a lower pressure bath with the plating solution passing through the hole causing plating within the inner surface of the hole.

    Abstract translation: 在衬底中形成通孔导体的方法，结构和系统包括：形成具有从半导体衬底的第一侧到第二侧的内表面的孔，并将半导体衬底的内表面镀覆到 当从半导体衬底的第一侧到半导体衬底的第二侧通过该孔强制电镀液时，形成导电元件。 孔从半导体晶片的第一侧到第二面以大致平面的电镀拓扑电镀。 通孔导体可以形成在电镀系统中，其中半导体衬底在较高压力浴和较低压力浴之间形成至少部分分隔，其中电镀液通过孔，从而在孔的内表面内镀覆电镀。

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