公开(公告)号：US20170317083A1

公开(公告)日：2017-11-02

申请号：US15652386

申请日：2017-07-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehoon LEE

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/10 ,  H01L29/778 ,  H01L29/267 ,  H01L29/423 ,  H01L29/20 ,  H01L21/8258

CPC classification number: H01L27/0922 ,  H01L21/8258 ,  H01L29/1054 ,  H01L29/2003 ,  H01L29/267 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7786

Abstract: A semiconductor device is provided as follows. A first buffer layer is disposed on a substrate including NMOS and PMOS regions. A first drain and a first source are disposed on the first buffer layer and have heterogeneous structures. A first channel is disposed between the first drain and the first source. A first gate electrode is disposed on the first channel. A second drain and a second source are disposed on the first buffer layer. A second channel is disposed between the second drain and the second source. The second channel includes a different material from the first channel. A second gate electrode is disposed on the second channel. The first drain, the first source, the first channel and the first gate electrode are disposed in the NMOS region. The second drain, the second source, the second channel and the second gate electrode are disposed in the PMOS region.

公开(公告)号：US09799568B2

公开(公告)日：2017-10-24

申请号：US15194720

申请日：2016-06-28

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L21/02 ,  H01L21/8238

CPC classification number: H01L21/8258 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/02395 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02617 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/8252 ,  H01L21/8256 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/7847 ,  H01L29/7849 ,  H01L29/785

Abstract: In one example, a device includes a p-type field effect transistor region and n-type field effect transistor region. The p-type field effect transistor region includes at least one fin including strained germanium. The n-type field effect transistor region also includes at least one fin including strained germanium.

公开(公告)号：US09793259B2

公开(公告)日：2017-10-17

申请号：US13472756

申请日：2012-05-16

Applicant: Michael A. Briere

Inventor： Michael A. Briere

IPC: H01L23/52 ,  H01L27/06 ,  H01L29/04 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778 ,  H01L21/8258 ,  H01L29/20

CPC classification number: H01L27/0617 ,  H01L21/8258 ,  H01L27/0688 ,  H01L29/045 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7786

Abstract: A III-nitride device that includes a silicon body having formed therein an integrated circuit and a III-nitride device formed over a surface of the silicon body.

公开(公告)号：US09786664B2

公开(公告)日：2017-10-10

申请号：US15040303

申请日：2016-02-10

Applicant: International Business Machines Corporation

Inventor： Lukas Czornomaz ,  Veeresh Vidyadhar Deshpande ,  Vladimir Djara ,  Jean Fompeyrine

IPC: H01L21/8239 ,  H01L27/092 ,  H01L29/201 ,  H01L29/161 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L27/0922 ,  H01L21/0206 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/8258 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/1033 ,  H01L29/161 ,  H01L29/20 ,  H01L29/201 ,  H01L29/42364 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

Abstract: A dual gate CMOS structure including a semiconductor substrate; a first channel structure including a first semiconductor material and a second channel structure including a second semiconductor material on the substrate. The first semiconductor material including SixGe1-x where x=0 to 1 and the second semiconductor material including a group III-V compound material. A first gate stack on the first channel structure includes: a first native oxide layer as an interface control layer, the first native oxide layer comprising an oxide of the first semiconductor material; a first high-k dielectric layer; a first metal gate layer. A second gate stack on the second channel structure includes a second high-k dielectric layer; a second metal gate layer. The interface between the second channel structure and the second high-k dielectric layer is free of any native oxides of the second semiconductor material.

公开(公告)号：US09786497B2

公开(公告)日：2017-10-10

申请号：US15162221

申请日：2016-05-23

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L21/02 ,  H01L29/267 ,  H01L21/302 ,  H01L21/311 ,  H01L29/06 ,  H01L29/165 ,  H01L21/762 ,  H01L29/04 ,  H01L21/8258 ,  H01L21/308

CPC classification number: H01L21/02532 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02538 ,  H01L21/02551 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/302 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/762 ,  H01L21/8258 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/165 ,  H01L29/267

Abstract: A semiconductor structure is provided by a process in which two aspect ratio trapping processes are employed. The structure includes a semiconductor substrate portion of a first semiconductor material having a first lattice constant. A plurality of first semiconductor-containing pillar structures of a second semiconductor material having a second lattice constant that is greater than the first lattice constant extend upwards from a surface of the semiconductor substrate portion. A plurality of second semiconductor-containing pillar structures of a third semiconductor material having a third lattice constant that is greater than the first lattice constant extend upwards from another surface of the semiconductor substrate portion. A spacer separates each first semiconductor-containing pillar structure from each second semiconductor-containing pillar structure. Each second semiconductor-containing pillar structure has a width that is different from a width of each first semiconductor-containing pillar structure.

公开(公告)号：US09773895B2

公开(公告)日：2017-09-26

申请号：US15133644

申请日：2016-04-20

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Balaji Padmanabhan ,  Prasad Venkatraman ,  Peter Moens ,  Mihir Mudholkar ,  Joe Fulton ,  Philip Celaya ,  Stephen St. Germain ,  Chun-Li Liu ,  Jason McDonald ,  Alexander Young ,  Ali Salih

IPC: H01L29/15 ,  H01L29/747 ,  H01L29/74 ,  H01L23/495 ,  H01L29/205 ,  H01L29/40 ,  H01L29/423 ,  H01L29/778 ,  H01L25/11 ,  H03K17/687 ,  H01L23/00 ,  H01L27/088 ,  H01L21/8258 ,  H01L27/06

CPC classification number: H01L29/747 ,  H01L21/8258 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/40 ,  H01L25/115 ,  H01L25/18 ,  H01L27/0629 ,  H01L27/088 ,  H01L27/0883 ,  H01L29/205 ,  H01L29/404 ,  H01L29/4238 ,  H01L29/7416 ,  H01L29/742 ,  H01L29/7786 ,  H01L29/7787 ,  H01L2224/0603 ,  H01L2224/40245 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2224/73221 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2924/00014 ,  H03K17/6874 ,  H03K2017/6878 ,  H03K2217/0009 ,  H03K2217/0018 ,  H01L2224/37099

Abstract: A half-bridge circuit can include a high-side HEMT, a high-side switch transistor, a low-side HEMT, and a low-side switch transistor. The die substrates of the HEMTs can be coupled to the sources of their corresponding switch transistors. In another aspect, a packaged electronic device for a half-bridge circuit can have a design that can use shorter connectors that help to reduce parasitic inductance and resistance. In a further aspect, a packaged electronic device for a half-bridge circuit can include more than one connection along the bottom of the package allows less lead connections along the periphery of the packaged electronic device and can allow for a smaller package.

公开(公告)号：US20170271334A1

公开(公告)日：2017-09-21

申请号：US15615245

申请日：2017-06-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Martin M. Frank ,  Renee T. Mo ,  Vijay Narayanan ,  John Rozen

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/0922 ,  H01L21/823807 ,  H01L21/823857 ,  H01L21/8258 ,  H01L27/092

Abstract: Semiconductor devices and methods of making the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region, the second semiconductor region being formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A gate dielectric layer is formed over one or more of the first and second channel regions. A nitrogen-containing layer is formed on the gate dielectric layer. A gate is formed on the gate dielectric.

公开(公告)号：US20170271211A1

公开(公告)日：2017-09-21

申请号：US15491989

申请日：2017-04-20

Applicant: Zing Semiconductor Corporation

Inventor： Deyuan Xiao

IPC: H01L21/8238 ,  H01L29/06 ,  H01L21/02 ,  H01L29/786 ,  H01L29/51 ,  H01L29/49 ,  H01L27/092 ,  H01L29/423

CPC classification number: H01L21/823807 ,  B82Y10/00 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02603 ,  H01L21/02639 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823857 ,  H01L21/8258 ,  H01L21/84 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1207 ,  H01L29/0673 ,  H01L29/1079 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/66227 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/7853 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696

Abstract: The present invention provides a method of manufacturing nanowire semiconductor device. In the active region of the PMOS the first nanowire is formed with high hole mobility and in the active region of the NMOS the second nanowire is formed with high electron mobility to achieve the objective of improving the performance of nanowire semiconductor device.

公开(公告)号：US09761445B2

公开(公告)日：2017-09-12

申请号：US15082500

申请日：2016-03-28

Applicant: Raytheon Company

Inventor： Jeffrey R. LaRoche ,  Kelly P. Ip ,  Thomas E. Kazior

IPC: H01L29/20 ,  H01L21/02 ,  H01L21/762 ,  H01L23/66 ,  H01L21/683 ,  H01L21/8258 ,  H01P11/00

CPC classification number: H01L21/0254 ,  H01L21/6835 ,  H01L21/7605 ,  H01L21/76251 ,  H01L21/76256 ,  H01L21/8258 ,  H01L23/66 ,  H01L29/2003 ,  H01L2221/68327 ,  H01L2224/32145 ,  H01L2924/0002 ,  H01P11/003 ,  H01L2924/00

Abstract: A method for providing a semiconductor structure includes: providing a structure having: layer comprising silicon, such as a layer of silicon or silicon carbide; a bonding structure; and silicon layer, the bonding structure being disposed between the layer comprising silicon and the silicon layer, the silicon layer being thicker than the layer comprising silicon; and, a Group III-V layer disposed on an upper surface of the layer comprising silicon; forming a Group III-V device in the III-V layer and a strip conductor connected to the device; removing silicon layer and the bonding structure to expose a bottom surface of layer comprising silicon; and forming a ground plane conductor on the exposed bottom surface of the layer comprising silicon to provide, with the strip conductor and the ground plane conductor, a microstrip transmission line.

公开(公告)号：US20170256546A1

公开(公告)日：2017-09-07

申请号：US15600972

申请日：2017-05-22

Applicant: International Business Machines Corporation

Inventor： Hemanth Jagannathan ,  Alexander Reznicek

IPC: H01L27/092 ,  H01L21/225 ,  H01L21/324 ,  H01L21/8238 ,  H01L21/8258 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/161 ,  H01L29/167 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L27/0924 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/2251 ,  H01L21/2258 ,  H01L21/324 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/8258 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/161 ,  H01L29/167 ,  H01L29/20 ,  H01L29/207 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7848

Abstract: A plurality of gate structures are formed straddling nFET semiconductor fins and pFET semiconductor fins which extend upwards from a surface of a semiconductor substrate. A boron-doped silicon germanium alloy material is epitaxially grown from exposed surfaces of both the nFET semiconductor fins and the pFET semiconductor fins not protected by the gate structures. An anneal is then performed. During the anneal, silicon and germanium from the boron-doped silicon germanium alloy material diffuse into the nFET semiconductor fins and act as an n-type dopant forming a junction in the nFET semiconductor fins. Since boron is a Group IIIA element it does not have any adverse effect. During the same anneal, boron from the boron-doped silicon germanium alloy material will diffuse into the pFET semiconductor fins to form a junction therein.